www.ti.com
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046G – JULY 1995 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
DESCRIPTION
This 12-bit to 24-bit multiplexed D-type latch is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16260 is used in applications in
which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or
demultiplexing address and data information in
microprocessor or bus-interface applications. This
device also is useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and
2B1-2B12) are available for address and/or data
transfer. The output-enable (OE1B, OE2B, and OEA)
inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank
control in the A-to-B direction.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B,
LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is
transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched
until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
FUNCTION TABLES
XXX
B TO A (OEB = H)
INPUTS
1B
2B
SEL
LE1B
LE2B
OEA
OUTPUT
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A0
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A0
X
X
X
X
X
H
Z
A TO B (OEA = H)
INPUTS
2
OUTPUTS
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
2B0
L
H
L
L
L
L
2B0
H
L
H
L
L
1B0
H
L
L
H
L
L
1B0
L
X
L
L
L
L
1B0
2B0
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
G1
C1
1
1D
8
23
1B1
1
C1
1D
6
2B1
C1
1D
C1
1D
To 11 Other Channels
3
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
DGG package
81
DL package
74
-65
V
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V to 3.6 V
IOH
IOL
High-level output current
Low-level output current
0.8
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
∆t/∆v Input transition rise or fall rate
TA
(1)
4
Operating free-air temperature
V
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
1.65 V to 3.6 V
1.65 V
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IOH = -12 mA
II(hold)
V
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
IOL = 24 mA
2.7 V
0.4
3V
0.55
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
VI = 0 to 3.6
V (2)
IOZ (3)
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
UNIT
1.2
IOL = 4 mA
IOL = 12 mA
II
MAX
VCC - 0.2
IOH = -4 mA
VOH
VOL
MIN TYP (1)
VCC
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
3.5
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
9
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN MAX
MIN MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
(1)
3.3
3.3
3.3
ns
tsu
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B
(1)
1.4
1.1
1.1
ns
th
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B
(1)
1.6
1.9
1.5
ns
(1)
This information was not available at the time of publication.
5
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
PARAMETER
tpd
(1)
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
(1)
1
5.4
5.1
1.2
4.3
A or B
(1)
1
5.6
5.2
1
4.4
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
A or B
B or A
LE
TYP
UNIT
ns
SEL
A
(1)
1
6.9
6.6
1.1
5.6
ten
OE
A or B
(1)
1
6.7
6.4
1
5.4
ns
tdis
OE
A or B
(1)
1
5.7
5
1.3
4.6
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
6
Power dissipation
capacitance
All outputs enabled
All outputs disabled
TEST CONDITIONS
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
37
41
(1)
4
7
UNIT
pF
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
7
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES046G – JULY 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
Input
1.5 V
1.5 V
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
1.5 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN74ALVCH16260DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH16260
SN74ALVCH16260DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH16260
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of