www.ti.com
FEATURES
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Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16952 contains two sets of D-type
flip-flops for temporary storage of data flowing in
either direction. This device can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A
or B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input,
provided that the clock-enable (CLKENAB or
CLKENBA) input is low. Taking the output-enable
(OEAB or OEBA) input low accesses the data on
either port.
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OEAB
1CLKAB
1CLKENAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16952 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
FUNCTION TABLE (1)
INPUTS
(1)
(2)
2
CLKENAB
CLKAB
OEAB
A
OUTPUT
B
H
X
L
X
B0 (2)
X
L
L
X
B0 (2)
L
↑
L
L
L
L
↑
L
H
H
X
X
H
X
Z
A-to-B data flow is shown; B-to-A data flow is similar, but uses
CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input conditions were
established
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
LOGIC SYMBOL(1)
1OEBA
56
54
1CLKENBA
1CLKBA
55
1
1OEAB
3
1CLKENAB
1CLKAB
2
29
2OEBA
31
2CLKENBA
2CLKBA
2OEAB
30
28
26
2CLKENAB
2CLKAB
1A1
27
5
EN3
G1
1C5
EN4
G2
2C6
EN9
G7
7C11
EN10
G8
8C12
3
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
2A3
2A4
2A5
2A6
2A7
2A8
(1)
4
52
51
8
49
9
48
10
47
12
45
13
44
14
43
15
9
12D
2A2
5D
11D
42
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
10
16
41
17
40
19
38
20
37
21
36
23
34
24
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
1CLKENAB
1CLKAB
1OEBA
1A1
3
54
2
55
56
1
5
One of Eight
Channels
C1
CE
1D
52
1CLKENBA
1CLKBA
1OEAB
1B1
C1
CE
1D
To Seven Other Channels
2CLKENAB
2CLKAB
2OEBA
2A1
26
31
27
30
29
28
15
One of Eight
Channels
C1
CE
1D
C1
CE
1D
To Seven Other Channels
4
42
2CLKENBA
2CLKBA
2OEAB
2B1
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DGG package
81
DGV package
86
DL package
(1)
(2)
(3)
(4)
V
V
°C/W
74
-65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = -100 µA
1.65 V to 3.6 V
1.65 V
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IOH = -12 mA
II(hold)
V
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
IOL = 24 mA
2.7 V
0.4
3V
0.55
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 0 to 3.6
V (2)
IOZ (3)
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
V
±5
VI = VCC or GND
VI = 2 V
UNIT
1.2
IOL = 4 mA
IOL = 12 mA
II
TYP (1) MAX
VCC - 0.2
IOH = -4 mA
VOH
VOL
MIN
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
3.5
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8.5
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
(1)
6
VCC = 2.5 V
± 0.2 V
MAX
MIN MAX
(1)
150
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN MAX
150
150
CLKEN high
(1)
3.3
3.3
3.3
CLK high or low
(1)
3.3
3.3
3.3
Data before CLK
(1)
1.7
1.9
1.5
CLKEN before CLK
(1)
1.2
1
1
Data after CLK
(1)
0.6
0.6
0.8
CLKEN after CLK
(1)
1.1
0.9
1.1
This information was not available at the time of publication.
UNIT
MHz
ns
ns
ns
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
FROM
(INPUT)
PARAMETER
VCC = 1.8 V
TO
(OUTPUT)
MIN
(1)
fmax
tpd
(1)
TYP
CLK
VCC = 2.5 V
± 0.2 V
MIN
VCC = 2.7 V
MAX
150
MIN
MAX
150
(1)
1
4.1
4.6
1
5.4
1
5.3
ten
OEBA or OEAB
A or B
tdis
OEBA or OEAB
A or B
(1)
MIN
UNIT
MAX
150
A or B
(1)
VCC = 3.3 V
± 0.3 V
MHz
1
3.9
ns
5.3
1
4.4
ns
4.4
1.1
4
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
Power dissipation
capacitance
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 0,
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
53
71
(1)
34
40
UNIT
pF
This information was not available at the time of publication.
7
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
9
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN74ALVCH16952DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH16952
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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