SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
FEATURES
•
•
•
•
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
TOE
D1
A1
GND
Y1
A2
VCC
D2
A3
GND
Y2
A4
D3
A5
GND
Y3
A6
VCC
D4
A7
GND
A8
Y4
LE
DESCRIPTION/ORDERING INFORMATION
This device contains four independent noninverting
buffers and an 8-bit noninverting bus transceiver and
D-type latch, designed for 1.65-V to 3.6-V VCC
operation.
The SN74ALVCH16973 is particularly suitable for
demultiplexing an address/data bus into a dedicated
address bus and dedicated data bus. The device is
used where there is asynchronous bidirectional
communication between the A and B data bus, and
the address signals are latched and buffered on the
Q bus. The control-function implementation minimizes
external timing requirements.
This device can be used as one 4-bit buffer, one 8-bit
transceiver, or one 8-bit latch. It allows data
transmission from the A bus to the B bus or from the
B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The transceiver
output-enable (TOE) input can be used to disable the
transceivers so that the A and B buses effectively are
isolated.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
DIR
B1
Q1
GND
B2
Q2
VCC
B3
Q3
GND
B4
Q4
B5
Q5
GND
B6
Q6
VCC
B7
Q7
GND
Q8
B8
LOE
ORDERING INFORMATION
PACKAGE (1)
TA
(1)
TOP-SIDE MARKING
Tube
SN74ALVCH16973DL
Tape and reel
SN74ALVCH16973DLR
TSSOP - DGG
Tape and reel
SN74ALVCH16973DGGR
ALVCH16973
TVSOP - DGV
Tape and reel
SN74ALVCH16973DGVR
VH973
SSOP - DL
-40°C to 85°C
ORDERABLE PART NUMBER
ALVCH16973
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of
the drivers.
The four independent noninverting buffers perform the Boolean function Y = D and are independent of the state
of DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
FUNCTION TABLES
INPUTS
TOE
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
A bus and B bus
isolation
INPUTS
2
LOE
LE
A
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
INPUT
D
OUTPUT
Y
L
L
H
H
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
48
1
LOE
LE
TOE
25
24
One of Eight Channels
C1
46
Q1
1D
A1
3
47
B1
To Seven Other Channels
One of Four Channels
D1
2
5
Y1
3
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O and D input ports (2)
-0.5
4.6
I/O and D input ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DGG package
70
DGV package
58
DL package
(1)
(2)
(3)
(4)
V
V
°C/W
63
-65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
MIN
MAX
1.65
3.6
Low-level input voltage
V
0.65 × VCC
1.7
V
2
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IBHH (3)
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
IBHHO
0.4
3V
0.55
±5
3.6 V
VI = 0.57 V
1.65 V
25
VI = 0.7 V
2.3 V
45
VI = 0.8 V
3V
75
VI = 1.07 V
1.65 V
-25
VI = 1.7 V
2.3 V
-45
3V
-75
1.95 V
200
2.7 V
300
3.6 V
500
1.95 V
-200
2.7 V
-300
3.6 V
-500
VI = 0 to VCC
(5)
2.7 V
VI = VCC or GND
VI = 2 V
IBHLO (4)
V
1.65 V to 3.6 V
IOL = 24 mA
IBHL (2)
1.2
IOL = 4 mA
IOL = 12 mA
VI = 0 to VCC
UNIT
VCC - 0.2
1.65 V
IOH = -12 mA
II
1.65 V to 3.6 V
MIN TYP (1) MAX
IOH = -4 mA
VOH
VOL
VCC
V
µA
µA
µA
µA
µA
IOZ (6)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND, IO = 0
3.6 V
30
µA
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
µA
Ci
Cio
Co
(1)
(2)
(3)
(4)
(5)
(6)
Control inputs
D
A ports
B ports
Q
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
3
4
4.5
4.5
3
pF
pF
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN
to VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
UNIT
MAX
tw
Pulse duration, LE high
2
2
2
ns
tsu
Setup time, data before LE↓
0.9
0.9
0.9
ns
th
Hold time, data after LE↓
0.9
0.9
0.9
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
ten
VCC = 1.8 V
TYP
MIN
MAX
MIN
MAX
D
Y
2.2
0.5
3.2
0.5
3
2.2
0.5
3.2
0.5
3
2.8
0.5
3.3
0.5
3
A
LE
Q
UNIT
A or B
B or A
2.2
0.5
3.2
0.5
3
LOE
Q
2.9
0.7
4.9
0.7
4.7
3
0.7
4.6
0.7
4.4
3.4
0.7
4.9
0.7
4.7
2.8
0.5
4.3
0.5
4.1
3.2
0.5
4.3
0.5
4.1
3.4
0.5
4.9
0.5
4.7
TOE
DIR
TOE
DIR
6
VCC = 3.3 V
± 0.3 V
TO
(OUTPUT)
LOE
tdis
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
A or B
Q
A or B
ns
ns
ns
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
OPERATING CHARACTERISTICS (1)
TA = 25°C
PARAMETER
Cpd (2)
(each output)
Cpd (Z)
Cpd (3)
(each LE)
(1)
(2)
(3)
Power dissipation
capacitance
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
UNIT
A outputs enabled,
Q outputs disabled,
One A output switching
One fA = 10 MHz,
One fB = 10 MHz,
TOE = GND,
LOE = VCC,
DIR = GND,
CL = 0 pF
12
14
19
B outputs enabled,
Q outputs disabled,
One B output switching
One fA = 10 MHz,
One fB = 10 MHz,
TOE = GND,
LOE = VCC,
DIR = GND,
CL = 0 pF
12
14
21
Q outputs enabled,
A and B I/Os isolated,
One Q output switching
One fA = 10 MHz,
One fLE = 20 MHz,
One fQ = 10 MHz,
TOE = VCC,
LOE = GND,
CL = 0 pF
11
13
19
One Y output switching,
A and B I/Os isolated,
Q outputs disabled
One fD = 10 MHz,
One fY = 10 MHz,
TOE = VCC,
LOE = VCC,
CL = 0 pF
7
8
12
A and B I/Os isolated,
Q outputs disabled,
One LE and one A data
input switching
One fA = 10 MHz,
One fLE = 20 MHz,
fQ not switching,
TOE = VCC,
LOE = VCC,
CL = 0 pF
4
5
11
pF
A and B I/Os isolated,
Q outputs disabled,
One LE input switching
fA not switching,
One fLE = 20 MHz,
fQ not switching,
TOE = VCC,
LOE = VCC,
CL = 0 pF
6
7
9
pF
Power dissipation
capacitance
Power dissipation
capacitance
TEST CONDITIONS
pF
Total device Cpd for multiple (m) outputs switching and (n) LE inputs switching = [m * Cpd (each output)] + [n * Cpd (each LE)].
Cpd (each output) is the Cpd for each data bit (input and output circuitry) when it operates at 10 MHz (Note: the LE is operating at
20 MHz in this test, but its ICC component has been subtracted).
Cpd (each LE) is the Cpd for the clock circuitry only when it operates at 20 MHz.
7
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
2 × VCC
2 × VCC
6V
30 pF
30 pF
50 pF
1 kΩ
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN74ALVCH16973DGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH16973
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of