SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
DGV, DW, OR PW PACKAGE
(TOP VIEW)
Operates From 1.65 V to 3.6 V
Max tpd of 3.3 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
DESCRIPTION/ORDERING INFORMATION
This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When
LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
PACKAGE (1)
TA
Tape and reel
SN74ALVCH373DWR
TSSOP - PW
Tape and reel
SN74ALVCH373PWR
VB373
TVSOP - DGV
Tape and reel
SN74ALVCH373DGVR
VB373
VFBGA - GQN
VFBGA - ZQN (Pb-free)
(1)
TOP-SIDE MARKING
SN74ALVCH373DW
SOIC - DW
-40°C to 85°C
ORDERABLE PART NUMBER
Tube
Tape and reel
SN74ALVCH373GQNR
SN74ALVCH373ZQNR
ALVCH373
VB373
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
TERMINAL ASSIGNMENTS
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
1
2
3
4
A
1Q
OE
VCC
8Q
B
2D
7D
1D
8D
7Q
C
3Q
2Q
6Q
B
D
4D
5D
3D
6D
C
E
GND
4Q
LE
5Q
D
E
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
LE
1
11
C1
1D
3
1D
To Seven Other Channels
Pin numbers shown are for the DGV, DW, and PW packages.
2
2
1Q
SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI
Input voltage range (2)
-0.5
4.6
V
VO
Output voltage range (2) (3)
-0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
mA
-50
mA
±50
mA
±100
mA
DGV package
92
DW package
58
GQN/ZQN package
78
PW package
V
-50
°C/W
83
-65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
5
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
1.65 V to 3.6 V
1.65 V
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IOH = -12 mA
II(hold)
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
1.65 V
25
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = VCC or GND,
IO = 0
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
(1)
(2)
Outputs
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
20
µA
3 V to 3.6 V
750
µA
V (2)
ICC
V
±5
VI = 1.07 V
VO = VCC or GND
Co
0.55
VI = 0.58 V
VI = 0 to 3.6
Data inputs
0.4
3V
3.6 V
IOZ
Control inputs
2.7 V
VI = VCC or GND
VI = 2 V
Ci
V
1.65 V to 3.6 V
IOL = 24 mA
UNIT
1.2
IOL = 4 mA
IOL = 12 mA
II
MAX
VCC - 0.2
IOH = -4 mA
VOH
VOL
MIN TYP (1)
VCC
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
4.5
pF
5
7.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
Pulse duration, LE high
3.8
3.3
3.3
3.3
ns
tsu
Setup time, data before LE↓
1.3
0.5
0.5
0.5
ns
th
Hold time, data after LE↓
0.5
1.3
1.7
1.2
ns
4
SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
D
tpd
LE
Q
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
1.7
6.3
1
2
6.1
1
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
MAX
MIN
MAX
4
4
1
3.6
3.8
3.7
1
3.3
UNIT
ns
ten
OE
Q
3.4
8.3
1.9
5.4
5.4
1.6
4.8
ns
tdis
OE
Q
1.6
7
1
4.4
4.4
1
4.4
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance per latch
Outputs enabled
Outputs disabled
TEST
CONDITIONS
CL = 0, f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
31
33
37
7
7
9
UNIT
pF
5
SN74ALVCH373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES116H – JULY 1997 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74ALVCH373DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VB373
Samples
SN74ALVCH373DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH373
Samples
SN74ALVCH373DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH373
Samples
SN74ALVCH373PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VB373
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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