www.ti.com
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus+™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
B-Port Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
UBE™ (Universal Bus Exchanger) Allows
Synchronous Data Exchange
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DLR package is
abbreviated to LR.
DESCRIPTION
This 9-bit, 4-port universal bus exchanger is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCHR16409 allows synchronous data
exchange between four different buses. Data flow is
controlled by the select (SEL0-SEL4) inputs. A
data-flow state is stored on the rising edge of the
clock (CLK) input if the select-enable (SELEN) input
is low. Once a data-flow state has been established,
data is stored in the flip-flop on the rising edge of
CLK if SELEN is high.
DGG OR DL PACKAGE
(TOP VIEW)
PRE
SEL0
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
SEL1
SEL2
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
SELEN
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
SEL4
SEL3
The data-flow control logic is designed to allow glitch-free data transmission.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce
overshoot and undershoot.
When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To
leave the high-impedance state, both PRE and SELEN must be low, and a clock pulse must be applied.
To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCHR16409 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC, UBE are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
FUNCTION TABLES
INPUTS
(1)
2
CLK
SEND PORT
OUTPUT
RECEIVE PORT
X
X
B0 (1)
X
L
L
X
H
H
↑
L
L
↑
H
H
H
X
B0 (1)
L
X
B0 (1)
Output level before the indicated steady-state input conditions
were established
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
DATA-FLOW CONTROL
INPUTS
DATA FLOW
PRE
SELEN
CLK
SEL0
SEL1
SEL2
SEL3
SEL4
H
X
X
X
X
X
X
X
L
H
↑
X
X
X
X
X
No change
L
L
↑
0
0
0
0
0
None, all I/Os off
L
L
↑
0
0
0
0
1
Not used
L
L
↑
0
0
0
1
0
Not used
L
L
↑
0
0
0
1
1
Not used
L
L
↑
0
0
1
0
0
Not used
L
L
↑
0
0
1
0
1
Not used
L
L
↑
0
0
1
1
0
Not used
L
L
↑
0
0
1
1
1
Not used
L
L
↑
0
1
0
0
0
2A to 1A and 1B to 2B
L
L
↑
0
1
0
0
1
2A to 1A
L
L
↑
0
1
0
1
0
2B to 1B
L
L
↑
0
1
0
1
1
2A to 1A and 2B to 1B
L
L
↑
0
1
1
0
0
1A to 2A and 1B to 2B
L
L
↑
0
1
1
0
1
1A to 2A
L
L
↑
0
1
1
1
0
1B to 2B
L
L
↑
0
1
1
1
1
1A to 2A and 2B to 1B
L
L
↑
1
0
0
0
0
1A to 1B and 2B to 2A
L
L
↑
1
0
0
0
1
1A to 1B
L
L
↑
1
0
0
1
0
2A to 2B
L
L
↑
1
0
0
1
1
1A to 1B and 2A to 2B
L
L
↑
1
0
1
0
0
1B to 1A and 2A to 2B
L
L
↑
1
0
1
0
1
1B to 1A
L
L
↑
1
0
1
1
0
2B to 2A
L
L
↑
1
0
1
1
1
1B to 1A and 2B to 2A
L
L
↑
1
1
0
0
0
2B to 1A and 2A to 1B
L
L
↑
1
1
0
0
1
1B to 2A
L
L
↑
1
1
0
1
0
2B to 1A
L
L
↑
1
1
0
1
1
2B to 1A and 1B to 2A
L
L
↑
1
1
1
0
0
1A to 2B and 1B to 2A
L
L
↑
1
1
1
0
1
1A to 2B
L
L
↑
1
1
1
1
0
2A to 1B
L
L
↑
1
1
1
1
1
1A to 2B and 2A to 1B
All outputs disabled
3
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
SELEN
56
1
PRE
55
28
SEL2
2
29
SEL0
SEL1
SEL3
Flow and Storage Control
27
30
SEL4
3
3
2Ax 1Ax
CLK
D
1A
1Ax
CLK
D
2A
CLK
D
1Bx 2Ax
2Bx 2Bx
3
1B
3
1Ax
1Ax
1Bx
2Bx
2Ax
1Bx
2Ax
1Bx
CLK
D
2B
2Bx
One of Nine Channels
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
Supply voltage range
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
4
V
V
V
-50
mA
-50
mA
±50
mA
±100
mA
DGG package
81
DL package
74
-65
UNIT
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
www.ti.com
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-2
VCC = 2.3 V
-6
VCC = 2.7 V
-8
mA
-12
VCC = 1.65 V
2
VCC = 2.3 V
6
VCC = 2.7 V
8
VCC = 3 V
(1)
V
0.35 × VCC
VCC = 3 V
IOL
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
12
-40
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
VOH
1.65 V to 3.6 V
1.2
IOH = -4 mA
2.3 V
1.9
2.3 V
1.7
3V
2.4
IOH = -8 mA
2.7 V
2
IOH = -12 mA
3V
2
IOL = 100 µA
MAX
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
2.3 V
0.55
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
±5
3.6 V
VI = 0.58 V
1.65 V
VI = 1.07 V
VI = 0.7 V
2.3 V
VI = 1.7 V
VI = 0.8 V
3V
VI = 2 V
UNIT
V
IOL = 2 mA
VI = VCC or GND
II(hold)
TYP (1)
VCC - 0.2
1.65 V
IOL = 6 mA
II
MIN
IOH = -2 mA
IOH = -6 mA
VOL
VCC
V
µA
25
-25
45
µA
-45
75
-75
VI = 0 to 3.6 V (2)
3.6 V
±500
IOZ (3)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µA
One input at VCC - 0.6 V,
Other inputs at VCC or GND
750
µA
∆ICC
3 V to 3.6 V
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8
pF
(1)
(2)
(3)
6
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
MIN
Clock frequency
tw
Pulse duration, CLK high or low
th
(1)
Setup time
Hold time
MIN
(1)
fclock
tsu
MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MAX
MIN
120
VCC = 3.3 V
± 0.3 V
MAX
MIN
120
120
(1)
4.2
4.2
3
A or B before CLK↑
(1)
1.9
1.9
1.4
SEL before CLK↑
(1)
5.1
4.2
3.5
SELEN before CLK↑
(1)
2.5
2.5
1.8
PRE before CLK↑
(1)
1
1
0.7
A or B after CLK↑
(1)
0.8
0.8
1
SEL after CLK↑
(1)
0
0
0
SELEN after CLK↑
(1)
0.5
0.5
0.8
UNIT
MAX
MHz
ns
ns
ns
This information was not available at the time of publication.
TIMING DIAGRAM
CLK
tsu
th
SELEN
tsu
SEL
(0-4)
th
tsu
Selected
Input Port
Selected
Output Port
th
tpd
CLK to Output
7
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
(1)
fmax
tpd
CLK
ten
CLK
CLK
tdis
(1)
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V
MAX
MIN
120
MAX
120
MIN
UNIT
MAX
120
MHz
A or B
(1)
1.5
6.9
7
1.5
6.2
ns
A or B
(1)
2.4
7.8
7.6
2
6.8
ns
(1)
2.3
7.1
6.4
2
6.1
(1)
2.8
7.7
7
2.5
6.4
A or B
PRE
MIN
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
8
Power dissipation
capacitance
All outputs enabled
All outputs disabled
TEST CONDITIONS
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
60
60
(1)
60
60
UNIT
pF
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
9
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
10
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
S1
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
0V
0V
tsu
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
3V
1.5 V
VOL + 0.3 V
tPZH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
2.7 V
1.5 V
tPZL
2.7 V
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
Output
1.5 V
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
VOH
1.5 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
11
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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