SN74ALVCHR16601GR

SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes Operates From 1.65 V to 3.6 V Max tpd of 4.4 ns at 3.3 V ±12-mA Output Drive at 3.3 V Outputs Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA DESCRIPTION/ORDERING INFORMATION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74ALVCHR16601DL Tape and reel SN74ALVCHR16601LR TSSOP - DGG Tape and reel SN74ALVCHR16601GR ALVCHR16601 TVSOP - DGV Tape and reel SN74ALVCHR16601VR VR601 SSOP - DL -40°C to 85°C ORDERABLE PART NUMBER Tube ALVCHR16601 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2004, Texas Instruments Incorporated SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. The outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. FUNCTION TABLE (1) INPUTS (1) (2) 2 LEAB CLKAB A OUTPUT B H X X X Z L H X L L X L H X H H H L L X X B0 (2) L L L ↑ L L L L L ↑ H H L L L L or H X B0 (2) CLKENAB OEAB X X A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA, LEBA, CLKBA, and CLKENBA. Output level before the indicated steady-state input conditions were established SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 1 OEAB CLKENAB CLKAB LEAB LEBA 56 55 2 28 30 CLKBA CLKENBA OEBA A1 29 27 CE 3 54 1D C1 CLK B1 CE 1D C1 CLK To 17 Other Channels ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC VI MIN MAX -0.5 4.6 V Except I/O ports (2) -0.5 4.6 V I/O ports (2) (3) -0.5 VCC + 0.5 V -0.5 VCC + 0.5 Supply voltage range Input voltage range range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range DGG package 64 DGV package 48 DL package 56 -65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V IOH High-level output current 0.8 VCC = 1.65 V -2 VCC = 2.3 V -6 VCC = 2.7 V -8 VCC = 3 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 4 mA -12 VCC = 1.65 V 2 VCC = 2.3 V 6 VCC = 2.7 V 8 VCC = 3 V (1) V mA 12 -40 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA VOH 1.65 V to 3.6 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3V 0.8 ±5 3.6 V VI = 0.58 V 1.65 V VI = 1.07 V VI = 0.7 V 2.3 V VI = 1.7 V VI = 0.8 V 3V VI = 2 V UNIT V IOL = 2 mA VI = VCC or GND II(hold) MAX VCC - 0.2 1.65 V IOL = 6 mA II MIN TYP (1) IOH = -2 mA IOH = -6 mA VOL VCC V µA 25 -25 45 µA -45 75 -75 VI = 0 to 3.6 V (2) 3.6 V ±500 IOZ (3) VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA One input at VCC - 0.6 V, Other inputs at VCC or GND 750 µA ∆ICC 3 V to 3.6 V Ci Control inputs VI = VCC or GND 3.3 V 4 pF Cio A or B ports VO = VCC or GND 3.3 V 8 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. 5 SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V MIN fclock tw Setup time th Hold time MAX VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN 150 (1) 3.3 3.3 3.3 CLK high or low (1) 3.3 3.3 3.3 Data before CLK↑ (1) 2.3 2.4 2.1 CLK high (1) 2 1.6 1.6 CLK low (1) 1.3 1.2 1.1 Data before LE↓ CLKEN before CLK↑ (1) 2 2 1.7 Data after CLK↑ (1) 0.7 0.7 0.8 CLK high (1) 1.3 1.6 1.4 CLK low (1) 1.7 2 1.7 (1) 0.3 0.5 0.6 Data after LE↓ UNIT MAX 150 LE high CLKEN after CLK↑ (1) MIN (1) Clock frequency Pulse duration tsu MAX VCC = 2.5 V ± 0.2 V MHz ns ns ns This information was not available at the time of publication. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 1.8 V TO (OUTPUT) MIN TYP (1) fmax tpd LEAB or LEBA B or A CLKAB or CLKBA (1) MIN MAX 150 (1) A or B VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN 150 1 4.8 5.1 (1) 1 5.5 (1) 1.2 5.9 UNIT MAX MHz 1 4.4 5.8 1 5.1 6.3 1.4 5.4 ns ten OEAB or OEBA B or A (1) 1.1 6.3 6.6 1.1 5.6 ns tdis OEAB or OEBA B or A (1) 1 4.2 5.1 1.6 4.7 ns This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd (1) 6 Power dissipation Outputs enabled capacitance Outputs disabled TEST CONDITIONS CL = 0, f = 10 MHz This information was not available at the time of publication. VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 56 63 (1) 12 13 UNIT pF SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES123I – SEPTEMBER 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) tPLZ VLOAD/2 VM tPZH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPHL VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ALVCHR16601DLG4 ACTIVE SSOP DL 56 74ALVCHR16601GRE4 ACTIVE TSSOP DGG 74ALVCHR16601GRG4 ACTIVE TSSOP 74ALVCHR16601LRG4 ACTIVE 74ALVCHR16601VRE4 20 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCHR16601VRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCHR16601DL ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCHR16601GR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCHR16601LR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCHR16601VR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALVCHR16601GR Package Package Pins Type Drawing TSSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ALVCHR16601LR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74ALVCHR16601VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCHR16601GR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ALVCHR16601LR SSOP DL 56 1000 346.0 346.0 49.0 SN74ALVCHR16601VR TVSOP DGV 56 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–
8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ALVCHR16601DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 SN74ALVCHR16601GR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 SN74ALVCHR16601LR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 SN74ALVCHR16601VR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VR601 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of