SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V VCC )
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V VCC)
Power Off Disables Outputs, Permitting
Live Insertion
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds VCC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16821 . . . WD PACKAGE
SN74ALVTH16821 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
description
The ’ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the
D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
description (continued)
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16821 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16821 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit section)
INPUTS
2
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
logic diagram (positive logic)
1OE
1CLK
1
56
One of Ten
Channels
1D1
C1
55
2
1D
1Q1
To Nine Other Channels
2OE
2CLK
28
29
One of Ten
Channels
2D1
C1
42
1D
15
2Q1
To Nine Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output current in the low state, IO: SN54ALVTH16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ALVTH16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, IO: SN54ALVTH16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
SN74ALVTH16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16821
SN74ALVTH16821
MIN
MAX
MIN
2.7
2.3
VCC
VIH
Supply voltage
2.3
High-level input voltage
1.7
VIL
VI
Low-level input voltage
IOH
High-level output current
IOL
∆t/∆v
TYP
TYP
2.7
1.7
0
VCC
5.5
–6
Low-level output current
0.7
0
VCC
V
V
5.5
V
–8
mA
6
8
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
18
24
Input transition rise or fall rate
10
10
Outputs enabled
UNIT
V
0.7
Input voltage
MAX
mA
ns/V
∆t/∆VCC
Power-up ramp rate
200
200
µs/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16821
SN74ALVTH16821
MIN
MAX
MIN
3.6
3
VCC
VIH
Supply voltage
3
High-level input voltage
2
VIL
VI
Low-level input voltage
IOH
High-level output current
IOL
∆t/∆v
TYP
TYP
3.6
2
0
5.5
0.8
0
V
VCC
V
5.5
V
–24
–32
mA
Low-level output current
24
32
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
Input transition rise or fall rate
10
10
Outputs enabled
VCC
UNIT
V
0.8
Input voltage
MAX
mA
ns/V
∆t/∆VCC
Power-up ramp rate
200
200
µs/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
VIK
VOH
VCC = 2.3 V,
VCC = 2.3 V to 2.7 V,
II = –18 mA
IOH = –100 µA
3V
VCC = 2
2.3
IOH = –6 mA
IOH = –8 mA
VCC = 2.3 V to 2.7 V,
VOL
VCC = 2
2.3
3V
Control inputs
VCC = 2.7 V,
VCC = 0 or 2.7 V,
II
Data inputs
Ioff
IBHL‡
IBHH§
SN54ALVTH16821
MIN TYP†
MAX
TEST CONDITIONS
VCC = 2.7 V
SN74ALVTH16821
MIN TYP†
MAX
–1.2
VCC–0.2
1.8
–1.2
V
1.8
IOL = 100 µA
IOL = 6 mA
0.2
0.2
0.4
IOL = 8 mA
IOL = 18 mA
0.4
IOL = 24 mA
VI = VCC or GND
0.5
VI = 5.5 V
VI = 5.5 V
VI = VCC
VI = 0
±1
±1
10
10
10
10
1
1
–5
–5
±100
VCC = 2.3 V,
VCC = 2.7 V,
VI = 1.7 V
VI = 0 to VCC
IEX||
VCC = 2.7 V,
VCC = 2.3 V,
VI = 0 to VCC
VO = 5.5 V
IOZ(PU/PD)k
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
IOZH
VCC = 2
2.7
7V
IOZL
7V
VCC = 2
2.7
Outputs high
ICC
VCC = 2.7 V,
IO = 0,
VI = VCC or GND
Outputs disabled
VCC = 2.5 V,
VCC = 2.5 V,
VI = 2.5 V or 0
VO = 2.5 V or 0
3.5
3.5
6.5
6.5
Co
V
0.5
VI or VO = 0 to 4.5 V
VI = 0.7 V
Ci
V
VCC–0.2
VCC = 0,
VCC = 2.3 V,
IBHLO¶
IBHHO#
UNIT
µA
µA
115
115
µA
–10
–10
µA
300
300
µA
–300
–300
µA
125
125
µA
±100
±100
µA
VO = 2.3 V,
VI = 0.7 V or 1.7 V
5
5
µA
VO = 0.5 V,
VI = 0.7 V or 1.7 V
5
–5
5
–5
µA
Outputs low
0.04
0.1
0.04
0.1
2.3
0.04
4.5
2.3
4.5
0.1
0.04
0.1
mA
pF
pF
† All typical values are at VCC = 2.5 V, TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
VIK
VOH
VCC = 3 V,
VCC = 3 V to 3.6 V,
II = –18 mA
IOH = –100 µA
VCC = 3 V
IOH = –24 mA
IOH = –32 mA
VCC = 3 V to 3.6 V,
VOL
VCC = 3 V
Control inputs
Ioff
IBHL‡
IBHH§
IBHLO¶
IBHHO#
IEX||
2
IOL = 100 µA
IOL = 16 mA
0.2
IOL = 24 mA
IOL = 32 mA
0.5
IOL = 48 mA
IOL = 64 mA
0.55
0.2
0.4
0.5
V
0.55
±1
±1
10
10
10
10
1
1
VCC = 3.6 V
VI = 0
VI or VO = 0 to 4.5 V
–5
VCC = 3.6 V,
VCC = 3 V,
V
V
VI = 5.5 V
VI = VCC
VCC = 3 V,
VCC = 3.6 V,
–1.2
UNIT
VCC–0.2
VI = VCC or GND
VI = 5.5 V
VCC = 0,
VCC = 3 V,
SN74ALVTH16821
MIN TYP†
MAX
–1.2
VCC–0.2
2
VCC = 3.6 V,
VCC = 0 or 3.6 V,
II
Data inputs
SN54ALVTH16821
MIN TYP†
MAX
TEST CONDITIONS
VI = 0.8 V
VI = 2 V
VI = 0 to VCC
VI = 0 to VCC
µA
–5
±100
µA
75
75
µA
–75
–75
µA
500
500
µA
–500
µA
–500
125
125
µA
±100
±100
µA
IOZ(PU/PD)k
VO = 5.5 V
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
IOZH
VCC = 3
3.6
6V
VO = 3 V,
VI = 0.8 V or 2 V
5
5
µA
IOZL
VCC = 3
3.6
6V
VO = 0.5 V,
VI = 0.8 V or 2 V
–5
5
–5
5
µA
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
Outputs high
0.07
0.1
0.07
Outputs low
3.2
5.5
3.2
5
0.07
0.1
0.07
0.1
Outputs disabled
∆ICCh
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VCC = 3.3 V,
VCC = 3.3 V,
Co
VI = 3.3 V or 0
VO = 3.3 V or 0
0.4
0.1
0.4
3.5
3.5
6
6
mA
mA
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k High-impedance state during power up or power down
h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16821
MIN
fclock
tw
Clock frequency
MAX
SN74ALVTH16821
MIN
150
Pulse duration, CLK high or low
tsu
time data before CLK↑
Setup time,
th
Hold time
time, data after CLK↑
MAX
150
1.6
1.5
Data high
1.6
1.5
Data low
2.1
2
Data high
0.4
0.3
Data low
1.1
1
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH16821
MIN
fclock
tw
Clock frequency
MAX
SN74ALVTH16821
MIN
150
Pulse duration, CLK high or low
tsu
Setup time,
time data before CLK↑
th
Hold time
time, data after CLK↑
MAX
150
1.6
1.5
Data high
1.6
1.5
Data low
1.6
1.5
Data high
1.1
1
Data low
1.1
1
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ALVTH16821
MIN
MAX
150
CLK
Q
OE
Q
OE
Q
SN74ALVTH16821
MIN
MAX
150
UNIT
MHz
1
4.2
1
4.1
1
4.5
1
4.4
1.5
4.7
1.5
4.6
1
4.2
1
4.1
1.5
4.6
1.5
4.5
1
5
1
4.9
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ALVTH16821
MAX
150
CLK
Q
OE
Q
OE
Q
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVTH16821
MIN
MAX
150
UNIT
MHz
1
3.6
1
3.5
1
3.6
1
3.5
1
4.2
1
4.1
1
3.7
1
3.6
1
4.9
1
4.8
1
4.8
1
4.6
ns
ns
ns
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
3V
3V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
1.5 V
3V
1.5 V
0V
0V
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
3V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
1.5 V
tPLZ
tPZL
1.5 V
tPLH
1.5 V
0V
3V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
0V
0V
tsu
Data
Input
1.5 V
Input
1.5 V
VOH
VOH – 0.3 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ALVTH16821DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16821
SN74ALVTH16821DLR
ACTIVE
SSOP
DL
56
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16821
SN74ALVTH16821GR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16821
SN74ALVTH16821VR
ACTIVE
TVSOP
DGV
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VT821
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
