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SN74AS1032ADE4

SN74AS1032ADE4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC14

  • 描述:

    IC GATE OR 4CH 2-INP 14SOIC

  • 数据手册
  • 价格&库存
SN74AS1032ADE4 数据手册
         SDAS072B − DECEMBER 1982 − REVISED JANUARY 1995 Driver Version of ′AS32 High Capacitive-Drive Capability Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54AS1032A . . . J PACKAGE SN74AS1032A . . . D OR N PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND description These devices contain four independent 2-input positive-OR buffers/drivers. They perform the Boolean functions Y = A + B or Y = A • B in positive logic. H X H X H H L L L 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A B A 2 1B 1A NC VCC 1Y NC 2A NC 2B FUNCTION TABLE (each gate) OUTPUT Y 14 SN54AS1032A . . . FK PACKAGE (TOP VIEW) The SN54AS1032A is characterized for operation over the full military temperature range of − 55°C to 125°C. The SN74AS1032A is characterized for operation from 0°C to 70°C. INPUTS 1 4B • • • NC − No internal connection logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 2 logic diagram (positive logic) ≥1 3 1A 1Y 1B 4 6 5 2A 2Y 2B 9 8 10 3A 3Y 3B 12 11 13 4A 4Y 4B 1 2 3 1Y 4 5 6 2Y 9 10 8 3Y 12 13 11 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. Copyright  1995, Texas Instruments Incorporated   !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1          SDAS072B − DECEMBER 1982 − REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS1032A . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74AS1032A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions‡ SN54AS1032A SN74AS1032A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −40 −48 mA 48 mA 70 °C High-level input voltage 2 2 IOL Low-level output current TA Operating free-air temperature −55 ‡ These high sink- or source-current devices are not recommended for use above 40 MHz. V 40 125 V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54AS1032A MIN TYP§ MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = −18 mA IOH = − 2 mA VCC = 4.5 V IOH = − 3 mA IOH = − 40 mA VOL VCC = 4.5 V II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO¶ VCC = 5.5 V, VCC = 5.5 V, ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, SN74AS1032A MIN TYP§ MAX −1.2 VCC − 2 2.4 −1.2 VCC − 2 2.4 3.2 V 3.2 V 2 IOH = − 48 mA IOL = 40 mA UNIT 2 0.25 IOL = 48 mA VI = 7 V 0.5 0.35 VI = 2.7 V VI = 0.4 V VO = 2.25 V VI = 4.5 V −50 V 0.1 0.1 20 20 µA −0.5 −0.5 mA −200 mA 11.5 mA −200 7.7 0.5 11.5 −50 7.7 mA VI = 0 14.7 24 14.7 24 mA § All typical values are at VCC = 5 V, TA = 25°C. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 •          SDAS072B − DECEMBER 1982 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54AS1032A tPLH tPHL A or B Y UNIT SN74AS1032A MIN MAX MIN MAX 1 7 1 6.3 1 7 1 6.3 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3          SDAS072B − DECEMBER 1982 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 3.5 V Input tPHZ 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output VOL 0.3 V 1.3 V 1.3 V VOL tPLH tPHL VOH 1.3 V 1.3 V [3.5 V 1.3 V tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOH Out-of-Phase Output (see Note C) 0.3 V [0 V 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-88730012A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-8873001DA OBSOLETE CFP W 14 TBD Call TI Call TI -55 to 125 SN54AS1032AJ OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125 SN74AS1032AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS1032A SN74AS1032ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS1032A SN74AS1032ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS1032A SN74AS1032AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS1032AN SN74AS1032ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS1032AN SNJ54AS1032AFK OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 SNJ54AS1032AJ OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AS1032A, SN74AS1032A : • Catalog: SN74AS1032A • Military: SN54AS1032A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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SN74AS1032ADE4 价格&库存

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