SN74AS286N




    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 • • • • • SN54AS286 . . . J PACKAGE SN74AS286 . . . D OR N PACKAGE (TOP VIEW) Generate Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bit Parity Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port Glitch-Free Bus During Power Up/Down Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs G H XMIT I PARITY ERROR PARITY I/O GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC F E D C B A SN54AS286 . . . FK PACKAGE (TOP VIEW) description H G NC VCC F The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading. XMIT NC I NC PARITY ERROR 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 E NC D NC C PARITY I/O GND NC A B The transmit (XMIT) control input is implemented specifically to accommodate cascading. When XMIT is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs ( A−I ) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. 4 NC − No internal connection The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches. The SN54AS286 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C. FUNCTION TABLE NUMBER OF INPUTS (A −I) THAT ARE HIGH XMIT PARITY I/O PARITY ERROR 0, 2, 4, 6, 8 l H H l L H h h H h l L h h L h l H 1, 3, 5, 7, 9 0, 2, 4, 6, 8 1, 3, 5, 7, 9 h = high input level H = high output level l = low input level L = low output level Copyright  1994, Texas Instruments Incorporated   !"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0 $#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'( ('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+ '+('!5 #" &.. ,&$&%+'+$(0 • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 logic symbol† A B C D E F G H I 8 2k 9 6 10 1 N2 11 PARITY I/O 12 13 1 2, 1 5 PARITY ERROR 2 4 3 XMIT EN1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) A B C D E F G H I PARITY I/O XMIT 8 9 10 11 12 13 5 1 2 4 6 3 Pin numbers shown are for the D, J, and N packages. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PARITY ERROR 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54AS286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74AS286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS286 VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 High-level output current 0.8 −2 −2 −12 −15 IOL Low-level output current PARITY ERROR 20 20 PARITY I/O 32 48 TA Operating free-air temperature PARITY I/O −55 125 UNIT V V 0.8 PARITY ERROR IOH SN74AS286 0 70 V mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK All outputs VOH PARITY I/O PARITY I/O II = − 18 mA IOH = − 2 mA VCC = 4.5 V IOH = − 3 mA IOH = − 12 mA IIH IIL All other inputs PARITY I/O§ All other inputs PARITY I/O§ All other inputs IO¶ ICC Transmit Receive SN74AS286 TYP‡ MAX MIN −1.2 VCC − 2 2.4 −1.2 VCC − 2 2.4 2.9 V V 2.4 0.35 0.5 0.35 0.5 IOL = 32 mA IOL = 48 mA 0.5 VI = 5.5 V VI = 7 V 0.1 0.1 VCC = 5.5 V 0.1 0.1 50 50 VCC = 5.5 V, VI = 2.7 V 20 20 −0.5 −0.5 VCC = 5.5 V, VI = 0.4 V −0.5 −0.5 VCC = 5.5 V, VO = 2.25 V VCC = 4.5 V UNIT 3 2.4 IOH = − 15 mA IOL = 20 mA PARITY I/O II MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, PARITY ERROR VOL SN54AS286 TYP‡ MAX TEST CONDITIONS V 0.5 −30 VCC = 5.5 V −112 −30 −112 30 43 30 43 35 50 35 50 mA µA A mA mA mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § For I/O ports, the parameters IIH and IIL include the off-state output current. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 switching characteristics (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any A − I PARITY I/O tPLH tPHL Any A − I PARITY ERROR tPLH tPHL PARITY I/O PARITY ERROR tPZH tPZL XMIT PARITY I/O tPHZ tPLZ XMIT PARITY I/O VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† SN54AS286 SN74AS286 MIN MAX MIN MAX 3 17 3 15 3 15 3 14 3 20 3 16.5 3 18 3 16.5 3 10 3 9 3 10 3 9 3 14 3 13 3 17 3 16 3 13 3 11.5 3 11 3 10 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT ns ns ns ns ns 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 APPLICATION INFORMATION Figure 1 shows a 32-bit parity generator/checker with output polarity switching, parity-error detection, and parity on every byte. 8 9 10 11 12 13 1 2 4 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 5 Byte 1 6 5 Byte 2 6 ′AS21 5 PARITY Byte 3 6 5 Byte 4 6 EVEN/ODD XMIT Pin numbers shown are for the D, J, and N packages. Figure 1. 32-Bit Parity Generator/Checker • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 APPLICATION INFORMATION Figure 2 shows a 90-bit parity generator/checker with XMIT on the last stage available for use with parity detection. H H 8 9 10 11 12 13 1 2 4 3 8 9 10 11 12 13 1 2 4 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 5 6 H ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 5 6 H ′AS286 8 9 10 11 12 13 1 2 4 H 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 H 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 H 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT ′AS286 8 9 10 11 12 13 1 2 4 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 5 6 ′AS286 5 6 8 9 10 11 12 13 1 2 4 3 5 6 ′AS286 5 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 8 9 10 11 12 13 1 2 4 H 3 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 6 ′AS286 5 ′AS286 8 9 10 11 12 13 1 2 4 H 3 ′AS286 A B PARITY C ERROR D E F G PARITY I/O H I XMIT 5 6 ′AS286 5 6 6 XMIT Pin numbers shown are for the D, J, and N packages. Figure 2. 90-Bit Parity Generator/Checker With Parity-Error Detection 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PARITY ERROR 6 PARITY I/O 



    

 
    SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 3.5 V Input tPZH 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output VOL 0.3 V 1.3 V 1.3 V VOL tPLH tPHL VOH 1.3 V 1.3 V [3.5 V 1.3 V tPHZ Waveform 2 S1 Open (see Note B) 1.3 V VOH Out-of-Phase Output (see Note C) 0.3 V [0 V 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuits and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AS286D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AS286 Samples SN74AS286N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74AS286N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of