SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
•
•
•
D OR N PACKAGE
(TOP VIEW)
Selects One of Two 4-Bit Data Sources and
Synchronously Stores Data With System
Clock
Applications:
− Dual Source for Operands and Constants
in Arithmetic Processor; Can Release
Processor Register Files for Acquiring
New Data
− Implements Separate Registers Capable
of Parallel Exchange of Contents, Yet
Retains External Load Capability
− Has Universal-Type Register for
Implementing Various Shift Patterns,
Including Compound Left-Right
Capability
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
B2
A2
A1
B1
C2
D2
D1
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
QB
QC
QD
CLK
WS
C1
description
The SN74AS298A is a quadruple 2-input multiplexer with storage that provides essentially the equivalent
functional capabilities of two separate MSI functions (SN74AS157 and ′AS175A) in a 16-pin package.
When the word-select (WS) input is low, word 1 (A1, B1, C1, D1) is applied to the flip-flops. A high input to WS
causes the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the
negative-going edge of the clock pulse.
The SN74AS298A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OUTPUTS†
INPUTS
WS
CLK
QA
QB
QC
QD
L
↓
a1
b1
c1
d1
H
↓
a2
b2
c2
d2
X
H
QA0
QB0
QC0
QD0
† a1, a2, etc. = the level of steady-state input at A1,
A2, etc.
QA0, QB0, etc. = the level of QA, QB, etc. entered
on the most recent ↓ transition of CLK
Copyright 1994, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
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1
SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
logic symbol†
WS
CLK
A1
A2
B1
B2
C1
C2
D1
D2
10
11
MUX
G1
C2
3
2
15
1, 2D
1, 2D
QA
4
14
1
QB
9
13
5
QC
7
12
6
QD
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A1
WS
A2
B1
3
10
1S
C1
2
15
QA
1R
4
1S
B2
C1
1
14
QB
1R
C1
9
1S
C2
C1
5
13
QC
1R
D1
7
1S
D2
C1
6
1R
CLK
2
11
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12
QD
SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−2
mA
IOL
TA
Low-level output current
20
mA
70
°C
High-level input voltage
2
Operating free-air temperature
V
V
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = − 18 mA
IOH = − 2 mA
VOL
II
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
VCC = 5.5 V,
VI = 2.7 V
VCC = 5.5 V,
VI = 0.4 V
VCC = 5.5 V,
VCC = 5.5 V
VO = 2.25 V
MIN
TYP‡
All others
All others
IO§
ICCH
V
V
0.35
0.5
V
0.1
mA
40
20
WS
IIL
UNIT
−1.2
VCC −2
WS
IIH
MAX
µA
A
−0.75
−0.5
−30
21
mA
−112
mA
33
mA
ICCL
VCC = 5.5 V
22
36
mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
MIN
MAX
UNIT
fclock
tw
Clock frequency
0
62
MHz
Pulse duration, CLK high or low
8
tsu
Setup time before CLK↓
th
Hold time after CLK↓
Data
4.5
WS
13
Data
3.5
WS
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•
1
ns
ns
ns
3
SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
PARAMETER
fmax
tPLH
TO
(OUTPUT)
MIN
MAX
62
CLK
tPHL
Q
UNIT
MHz
2
9
1
11
ns
APPLICATION INFORMATION
This versatile multiplexer can be connected to operate as a shift register that can shift n places in a single clock pulse.
Figure 1 illustrates a BCD shift register that shifts an entire 4-bit BCD digit in one clock pulse.
Parallel Load
WS
CLK
SN74AS298A
SN74AS298A
SN74AS298A
G1
C2
G1
C2
A1
1, 2D
A2
1, 2D
B1
B2
C1
C2
D1
D2
MUX
G1
C2
MUX
MUX
QA
QB
QC
QD
A1
1, 2D
A2
1, 2D
B1
B2
C1
C2
D1
D2
Digit 1
QA
QB
QC
QD
Digit 2
A1
A2
B1
B2
C1
C2
D1
D2
1, 2D
1, 2D
QA
QB
QC
QD
Digit 3
Figure 1. BCD Shift Register
When WS is high and the registers are clocked, the content of register 1 is transferred (shifted) to register 2, etc.,
effectively shifting the BCD digits one position. This application also retains a parallel-load capability, which means
that new BCD data can be entered into the entire register with one clock pulse. This arrangement can be modified
to perform the shifting of binary data for any number of bit locations.
Another function that can be implemented is a register designed specifically for supporting multiplier or division
operations (see Figure 2).
When WS is low and the register is clocked, the outputs of the arithmetic / logic units (ALUs) are shifted one place.
When WS is high and the registers are clocked, the data is shifted two places.
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•
SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
APPLICATION INFORMATION
SN74AS298A
MUX
G1
C2
WS
CLK
A1
A2
B1
B2
C1
C2
D1
D2
F0
′AS181A
F1
F2
1, 2D
1, 2D
QA
QB
QC
QD
F3
SN74AS298A
MUX
G1
C2
A1
A2
B1
B2
C1
C2
D1
D2
F0
′AS181A
F1
F2
1, 2D
1, 2D
QA
QB
QC
QD
F3
Figure 2. 1-Place / 2-Place Shift Register
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5
SDAS219B − DECEMBER 1983 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
From Output
Under Test
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
3.5 V
Input
tPZH
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
VOL
0.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
[3.5 V
1.3 V
tPHZ
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
0.3 V
[0 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
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•
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AS298AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AS298A
SN74AS298AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74AS298AN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of