SN74AUC16501DGGR

    
 

  
 
SCES418 – DECEMBER 2002 D Member of the Texas Instruments D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Widebus Family Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 2 ns at 1.8 V Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA description/ordering information This 18-bit universal bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). ORDERING INFORMATION PACKAGE† TA –40°C to 85°C ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74AUC16501DGGR AUC16501 TVSOP – DGV Tape and reel SN74AUC16501DGVR MH501 VFBGA – GQL Tape and reel SN74AUC16501GQLR MH501 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2002, Texas Instruments Incorporated    !"# $ %& '# "$  (&)*%"# +"#',  +&%#$ % ! # $('%%"#$ (' #-' #' !$  '."$ $# &!'#$ $#"+" + /" "#0,  +&%# ( %'$$1 +'$ # '%'$$" *0 %*&+' #'$#1  "** (" "!'#' $, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
    
 

  
 
SCES418 – DECEMBER 2002 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. GQL PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 A B C D 1 2 3 4 5 6 A A1 LEAB OEAB GND CLKAB B1 B A3 A2 GND GND B2 B3 C A5 A4 B5 A7 A6 VCC GND B4 D VCC GND B6 B7 E A9 A8 B8 B9 F A10 A11 B11 B10 G A12 A13 GND GND B13 B12 H A14 A15 B14 J A16 A17 VCC GND B15 H VCC GND B17 B16 J K A18 OEBA LEBA GND CLKBA B18 E F G K FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X H L L X B0‡ B0§ † A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low § Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
 

  
 
SCES418 – DECEMBER 2002 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels Pin numbers shown are for the DGG and DGV packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    
 

  
 
SCES418 – DECEMBER 2002 recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V High-level High level input in ut voltage VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL Input voltage VO O tp t voltage Output oltage ∆t/∆v 2.7 Low-level Low level out output ut current V 1.7 0 0.35 × VCC V 0.7 V Active state 0 3-state 0 VCC 3.6 V VCC = 1.4 V VCC = 1.65 V High-level High level out output ut current V 3.6 VCC = 2.3 V VCC = 0.8 V IOL 0.8 VCC 0.65 × VCC UNIT 0 VCC = 0.8 V VCC = 1.1 V IOH MAX VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V Low-level Low level input in ut voltage VI MIN –0.7 –3 –5 –9 0.7 VCC = 1.1 V VCC = 1.4 V 3 VCC = 1.65 V VCC = 2.3 V 8 Input transition rise or fall rate mA –8 5 mA 9 20 ns/V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
 

  
 
SCES418 – DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –0.7 mA VOH VOL II Ioff Control inputs MIN 0.8 V to 2.7 V VCC–0.1 0.8 V MAX UNIT 0.55 IOH = –3 mA IOH = –5 mA 1.1 V 0.8 1.4 V 1 IOH = –8 mA IOH = –9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.2 0.8 V 0.25 IOL = 3 mA IOL = 5 mA 1.1 V 0.3 1.4 V 0.4 IOL = 8 mA IOL = 9 mA 1.65 V 0.45 2.3 V 0.6 0.8 V to 2.7 V ±5 µA ±10 µA ±10 µA 20 µA VI = VCC or GND VI or VO = 2.7 V IOZ‡ ICC VO = VCC or GND VI = VCC or GND, Ci VI = VCC or GND VO = VCC or GND Cio TYP† VCC 0 2.7 V IO = 0 0.8 V to 2.7 V V 2.5 V 3.5 4.5 pF 2.5 V 6 7.5 pF † All typical values are at TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V TYP fclock Clock frequency tw Pulse duration tsu Setup S t time th Hold time VCC = 1.2 V ± 0.1 V MIN 85 MAX VCC = 1.5 V ± 0.1 V MIN 150 MAX VCC = 1.8 V ± 0.15 V MIN 250 MAX VCC = 2.5 V ± 0.2 V MIN 300 350 LE high 5.8 4 1.7 1.5 1.5 CLK high or low 5.8 4 1.7 1.5 1.5 Data before CLK↑ 0.2 0.6 0.6 0.6 0.6 CLK high 0.1 0.4 0.4 0.3 0.3 CLK low 0.1 0.4 0.4 0.3 0.3 0.3 1.2 1.1 0.9 0.9 1.3 1.5 1.3 1.2 1.2 Data before LE↓ Data after CLK↑ Data after LE↓ CLK high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns 5 
    
 

  
 
SCES418 – DECEMBER 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP fmax A or B tpd LE tpd CLK tdis ten tdis MIN MAX 85 tpd ten VCC = 1.2 V ± 0.1 V B or A A or B OEAB B OEBA A VCC = 1.5 V ± 0.1 V MIN 150 MAX VCC = 1.8 V ± 0.15 V MIN TYP 250 VCC = 2.5 V ± 0.2 V MAX MIN 300 UNIT MAX 350 MHz 8.5 0.9 4 1 2.8 0.3 2 2.8 0.1 2.3 ns 9.8 1.6 6.3 1 4.1 0.9 2.5 3.8 0.7 3 ns 9.2 1.5 3.8 0.7 3.1 0.9 2.2 3.3 0.6 2.7 ns 9.7 1.6 3 1.1 3.2 1 1.8 3.4 0.8 2.8 ns 15 3.6 5.3 0.9 5.7 1.7 2.4 3.2 1 3.1 ns 11 1.7 5.7 1 3.7 1 2.2 3.7 0.7 3 ns 18 3.5 7.5 1.4 5.4 2 3.5 5.2 0.9 3 ns operating characteristics for transparent mode, TA = 25°C TEST CONDITIONS PARAMETER Cpd† (each bit) Power dissipation capacitance Outputs enabled, 1 output switching 1 fdata = 10 MHz, fclk = VCC or GND, 1 fout = 10 MHz, OEAB = VCC, OEBA = GND, LE = VCC, CL = 0 pF VCC = 0.8 V TYP 30 VCC = 1.2 V TYP VCC = 1.5 V TYP 31 33 VCC = 1.8 V TYP 36 VCC = 2.5 V TYP 44 UNIT pF 1 fdata = 10 MHz, fclk = VCC or GND, Cpd Power 1 fout = not Outputs dissipation switching, 9 9 10 12 16 pF (each disabled capacitance OEAB = GND, bit) OEBA = VCC, LE = VCC, CL = 0 pF † Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (the clock is operating at 10 MHz in this test, but its ICC component has been subtracted out). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
 

  
 
SCES418 – DECEMBER 2002 operating characteristics for clocked mode, TA = 25°C† TEST CONDITIONS PARAMETER Cpd‡ (each bit) Cpd (Z) Cpd§ (each clock) VCC = 0.8 V TYP VCC = 1.2 V TYP VCC = 1.5 V TYP VCC = 1.8 V TYP VCC = 2.5 V TYP UNIT Power dissipation capacitance Outputs enabled, 1 output switching 1 fdata = 5 MHz, 1 fclk = 10 MHz, 1 fout = 5 MHz, OEAB = VCC, OEBA = GND, LE = GND, CL = 0 pF Power dissipation capacitance Outputs disabled, 1 clock and 1 data switching 1 fdata = 5 MHz, 1 fclk = 10 MHz, fout = not switching, OEAB = GND, OEBA = VCC, LE = GND, CL = 0 pF 8 8 9 10 13 pF Outputs disabled, clock only switching 1 fdata = 0 MHz, 1 fclk = 10 MHz, fout = not switching, OEAB = GND, OEBA = VCC, LE = GND, CL = 0 pF 31 32 32 34 39 pF Power dissipation capacitance 29 30 31 35 43 pF † Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)} ‡ Cpd (each bit) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (the clock is operating at 10 MHz in this test, but its ICC component has been subtracted out). § Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
    
 

  
 
SCES418 – DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND CL 15 pF 15 pF 15 pF 30 pF 30 pF VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V RL 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VCC/2 VOL tPHL VOH Output tPLZ VCC VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH VCC/2 VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC/2 tPZL VOH VCC/2 Output VCC Output Control VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–
8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated