SN74AUC1G125DBVR

SN74AUC1G125 SCES382M – MARCH 2002 – REVISED AUGUST 2022 SN74AUC1G125 Single Bus Buffer Gate With 3-State Output 1 Features 3 Description • • • • • The SN74AUC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. • • • • Optimized for 1.8-V operation ±8-mA output drive at 1.8 V Maximum tpd of 2.5 ns at 1.8 V, 30 pF load Wide operating voltage range of 0.8 V to 2.7 V Over-voltage tolerant I/Os support up to 3.6 V, independent of VCC Available in the Texas Instruments NanoFree™ package Ioff feature supports partial power down mode and back drive protection Low power consumption, 10-µA maximum ICC Latch-up performance exceeds 100 mA per JESD 78, Class II 2 Applications • • • Redrive digital signals Enable or disable a digital signal Drive transmission lines with logic The AUC logic family is specifically designed for speed and is optimized for operation between 1.65-V and 1.95-V VCC. With an optimal supply and 15-pF load the device can operate at over 250 MHz, or 500 Mbps. The unique output structure of the AUC family provides great signal integrity without the need for external termination when driving 50- to 65-Ω transmission lines of moderate length (less than 15 cm). See Application of the Texas Instruments AUC Sub-1-V Little Logic Devices for more details on this technology. This device is available in the popular SOT-23 and SC70 packages, as well as the advanced NanoFree™ DSBGA package. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. Package Information(1) PART NUMBER SN74AUC1G125 (1) OE A PACKAGE BODY SIZE (NOM) DBV (SOT-23, 5) 2.90 mm × 1.60 mm DCK (SC70, 5) 2.00 mm × 1.25 mm YZP (DSBGA, 5) 1.39 mm × 0.89 mm For all available packages, see the orderable addendum at the end of the data sheet. 1 4 2 Y Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Switching Characteristics: CL = 15 pF........................ 6 6.7 Switching Characteristics: CL = 30 pF........................ 6 6.8 Operating Characteristics........................................... 6 6.9 Typical Characteristics................................................ 7 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Application.................................................... 11 10 Power Supply Recommendations..............................12 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 11.2 Layout Example...................................................... 13 12 Device and Documentation Support..........................14 12.1 Documentation Support.......................................... 14 12.2 Receiving Notification of Documentation Updates..14 12.3 Support Resources................................................. 14 12.4 Trademarks............................................................. 14 12.5 Electrostatic Discharge Caution..............................14 12.6 Glossary..................................................................14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (June 2017) to Revision M (August 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document .................1 • Updated the Features section, Applications section, and Device Information table........................................... 1 • Changed the YZP (DSBGA, 5) body size from:1.75 mm × 1.25 mm to:1.39 mm × 0.89 mm ............................1 • Added the Application and Implementation, Application Information, Typical Application, Power Supply Recommendations, Layout, Layout Guidelines, and Layout Examples sections............................................... 1 • Updated the Pin Configuration and Functions section........................................................................................3 • Updated the ESD Ratings section...................................................................................................................... 4 • Updated the Thermal Information section...........................................................................................................5 Changes from Revision K (April 2007) to Revision L (June 2017) Page • Deleted DRY package throughout data sheet.................................................................................................... 1 • Added Applications, Device Information table, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...................................................................................................1 • Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data sheet .......................................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 5 Pin Configuration and Functions OE 1 A 2 GND 3 5 4 OE 1 A 2 GND 3 5 VCC 4 Y VCC Figure 5-2. DCK Package, 5-Pin SC70 (Top View) Y Figure 5-1. DBV Package, 5-Pin SOT-23 (Top View) Table 5-1. Pin Functions PIN NAME DBV, DCK TYPE(1) DESCRIPTION A 2 I Logic input GND 3 G Ground OE 1 I Active-low output enable VCC 5 P Positive supply Y 4 O Output (1) I = input, O = output, P = power, G = ground 1 2 C GND Y B A A OE VCC   Not to scale Figure 5-3. YZP Package, 5-Pin DSBGA (Bottom View) Legend Input Power Ground Output Table 5-2. Pin Functions PIN NO. NAME TYPE(1) DESCRIPTION A1 OE I Output enable, active low A2 VCC P Positive supply B1 A I Logic input C1 GND G Ground C2 Y O Output (1) I = input, O = output, P = power, G = ground Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 3 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX UNIT Supply voltage –0.5 3.6 V voltage(2) –0.5 3.6 V –0.5 3.6 V –0.5 VI Input VO Voltage range applied to any output in the high-impedance or power-off state(2) range(2) VO Output voltage VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) Storage temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Machine Model (A115-A) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See (1) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V MIN MAX UNIT 0.8 2.7 V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 0.8 V VIL 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V IOH 4 Low-level input voltage V High-level output current VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 Submit Document Feedback mA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 6.3 Recommended Operating Conditions (continued) See (1) MIN IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MAX VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V 9 VCC = 0.8 V to 1.6 V 20 VCC = 1.65 V to 1.95 V 10 VCC = 2.3 V to 2.7 V (1) UNIT mA ns/V 3 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs 6.4 Thermal Information THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) YZP (DSBGA) 5 PINS 5 PINS 5 PINS 220.7 262.5 144.5 °C/W UNIT RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 123.9 181.4 1.4 °C/W RθJB Junction-to-board thermal resistance 123.20 153.4 47.6 °C/W ΨJT Junction-to-top characterization parameter 58.3 67.60 0.6 °C/W ΨJB Junction-to-board characterization parameter 122.5 152.80 47.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II A or OE input TEST CONDITIONS VCC MIN TYP(1) MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA IOZ VO = VCC or GND 2.7 V ±10 µA ICC VI = VCC or GND 0.8 V to 2.7 V 10 µA CI VI = VCC or GND IO = 0 2.5 V 2.5 pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 5 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 6.5 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Co (1) VO = VCC or GND VCC MIN TYP(1) 2.5 V 5.5 MAX UNIT pF All typical values are at TA = 25°C. 6.6 Switching Characteristics: CL = 15 pF over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 7-1) VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN tpd A Y 4.7 0.8 3.6 0.4 2.3 ten OE Y 5.4 0.7 4.1 0.5 2.6 tdis OE Y 4.8 1.4 4.3 1.4 4 PARAMETER VCC = 2.5 V ± 0.2 V UNIT TYP MAX MIN MAX 0.6 1 1.5 0.5 1.3 ns 0.6 1.1 1.8 0.5 1.4 ns 1.5 2.2 2.9 0.9 2.2 ns 6.7 Switching Characteristics: CL = 30 pF over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 7-1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE tdis OE PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V UNIT MIN TYP MAX MIN MAX 0.7 1.5 2.5 0.9 1.7 ns Y 1 1.6 2.6 1.1 1.9 ns Y 1.8 2.2 3.1 0.8 1.7 ns 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP 14 14 14 15 16 1.5 1.5 1.5 2 2.5 f = 10 MHz UNIT pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 6.9 Typical Characteristics 0.8 2.7 0.7 2.4 0.6 0.5 0.4 0.3 0.2 VCC = 0.8 V VCC = 1.8 V VCC = 2.7 V 0.1 0 0 2 4 6 8 10 12 14 16 Output Low-State Current (I OL, mA) 18 20 Output Hi-Z State Leakage Current (IOZ, nA) Figure 6-1. Output Low-State Voltage Across Output Current, 0.8-, 1.8-, and 2.7-V Supply Output High-State Voltage (VOH, V) Output Low-State Voltage (VOL, V) TA = 25°C 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 -20 VCC = 0.8 V VCC = 1.8 V VCC = 2.7 V -18 -16 -14 -12 -10 -8 -6 -4 Output High-State Current (I OH, mA) -2 0 Figure 6-2. Output High-State Voltage Across Output Current, 0.8-, 1.8-, and 2.7-V Supply 8 VCC = 0.8 V VCC = 1.8 V VCC = 2.7 V 7 6 5 4 3 2 1 0 -1 -2 -3 0 0.3 0.6 0.9 1.2 1.5 1.8 Output Voltage (V O, V) 2.1 2.4 2.7 Figure 6-3. Output High-Impedance State Leakage Current Across Output Voltage, 0.8-, 1.8-, and 2.7-V Supply Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 7 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 7 Parameter Measurement Information TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tW tsu VCC Input VCC/2 VCC/2 th VCC Data Input VCC/2 VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPLH VOH Output VCC/2 VOL tPHL VCC/2 0V VCC VCC/2 tPZH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VCC/2 tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL tPHL VCC/2 VCC Output Control VOL + VD VOL tPHZ VCC/2 VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, slew rate ³ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 7-1. Load Circuit and Voltage Waveforms 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 8 Detailed Description 8.1 Overview The SN74AUC1G125 bus buffer gate is operational from 0.8-V to 2.7-V VCC, but is optimized for 1.65-V to 1.95-V VCC operation. This device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram OE A 1 4 2 Y Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 ULTTL CMOS Outputs This device includes ultra-low-voltage transistor-transistor logic (ULTTL) output drivers. ULTTL outputs are balanced, indicating that the device can sink and source similar currents. They are also specially designed for applications requiring high-speed, low power consumption, and optimal signal integrity while minimizing switching noise. The ULTTL output driver changes impedance during transition to maximize transition rate while limiting ringing and transmission line reflections. The output is optimized for operation with a direct connection to a 50- to 65-Ω controlled impedance transmission line of up to 15 cm, although it can operate with acceptable signal integrity for controlled impedances of between 30 and 70 Ω. The outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected. 8.3.2 Standard CMOS Inputs This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in Implications of Slow or Floating CMOS Inputs. Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a 10-kΩ resistor, however, is recommended and will typically meet all requirements. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 9 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 8.3.3 Partial Power Down (Ioff) This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage current at each output is defined by the Ioff specification in the Electrical Characteristics table. 8.3.4 Clamp Diode Structure Figure 8-2 shows the inputs and outputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC Logic Input -IIK Output -IOK GND Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74AUC1G125. Table 8-1. Function Table INPUTS(1) (1) (2) 10 OE A OUTPUT(2) Y L H H L L L H X Z L = Low Voltage Level, H = High Voltage Level, X = Do Not Care L = Driving Low, H = Driving High, Z = High Impedance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information In this application, the SN74AUC1G125 is used to control a high-speed digital signal. The output enable (OE) input is connected to the system controller and allows the output to be disabled. Not shown is a 10-kΩ pull-down resistor which will ensure that the output will return to the low state when placed in the high-impedance mode of operation. 9.2 Typical Application System Controller OE Data A Y Output Figure 9-1. Application Block Diagram 9.2.1 Design Requirements • • • • All signals in the system operate at 1.8 V ± 0.15 V Input signals transition faster than 10 ns/V Y output is enabled when OE is LOW Output transmission line impedance should be between 50 and 65 Ω 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the output tranmission line is less than 15 cm in total length for optimal signal integrity results. For the best signal integrity, avoid sharp turns, stubs, and branches. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 11 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 9.2.3 Application Curves 2.2 ZO = 70 2.0 1.8 1.6 ZO = 30
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 110 111 112 113 114 115 116 117 118 119 120 Figure 9-2. Simulated Output Voltage Waveforms for AUC Family Directly Driving Short (< 15 cm) Transmission Lines With Characteristic Impedances from 30 to 70 Ω (Volts vs Nanoseconds) 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation VCC Bypass capacitor placed close to the device 0.1
F Unused input tied directly to GND Avoid 90° corners for signal lines OE 1 A 2 GND 3 5 4 GND 0.1
F Avoid 90° corners for signal lines OE A1 A B1 A2 Bypass capacitor placed close to the device VCC VCC 50 controlled impedance Y GND Figure 11-1. Example Layout for DCK Package C1 C2 Y Figure 11-2. Example Layout for YZP Package Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 13 SN74AUC1G125 www.ti.com SCES382M – MARCH 2002 – REVISED AUGUST 2022 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, Implications of Slow or Floating CMOS Inputs application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks NanoFree™ is a trademark of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74AUC1G125 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74AUC1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U25R Samples 74AUC1G125DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U25R Samples SN74AUC1G125DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U25R Samples SN74AUC1G125DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (UM5, UMF, UMR) Samples SN74AUC1G125YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UMN Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of