SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
FEATURES
7
PRE
Q
3
6
CLR
GND
4
5
Q
8
7
6
4
5
See mechanical drawings for dimensions.
VCC
PRE
CLR
Q
VCC
8
4
YZP OR YZT PACKAGE
(BOTTOM VIEW)
GND
Q
D
CLK
Q
2
1
2
3
5
D
CLK
D
Q
GND
Q
VCC
D
8
3
1
CLK
CLK
RSE PACKAGE
(TOP VIEW)
6
DCU PACKAGE
(TOP VIEW)
2
DCT PACKAGE
(TOP VIEW)
CLR
•
•
•
7
•
Low Power Consumption, 10-μA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.5 ns at 1.8 V
PRE
•
4 5
3 6
2 7
1 8
Q
CLR
PRE
VCC
GND
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
ORDERING INFORMATION
TA
PACKAGE
–40°C to 85°C
(1)
(2)
(3)
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUC1G74YZPR
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZT (Pb-free)
Reel of 3000
SN74AUC1G74YZTR
QFN – RSE
Reel of 3000
SN74AUC1G74RSER
UP
SSOP – DCT
Reel of 3000
SN74AUC1G74DCTR
U74_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC1G74DCUR
U74_
_ _ _UP_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP/YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
L
H
X
X
H
Q
L
X
L
X
X
L
H
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
LOGIC DIAGRAM (POSITIVE LOGIC)
CLR
CLK
6
1
C
C
C
3
Q
TG
C
C
C
C
D
PRE
A.
2
2
TG
TG
TG
C
C
C
7
Pin numbers shown are for the DCT, DCU, YZP, and YZT packages only.
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5
Q
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
3.6
V
VI
Input voltage range (2)
–0.5
3.6
V
–0.5
3.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±100
mA
Continuous current through VCC or GND
Package thermal impedance (3)
θJA
Tstg
(1)
(2)
(3)
DCT package
220
DCU package
227
RSE package
253
YZP/YZT package
102
Storage temperature range
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
0.8
2.7
UNIT
V
VCC
0.65 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
V
1.7
VCC = 0.8 V
0
0.35 × VCC
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V to 2.7 V
IOH
High-level output current
IOL
Low-level output current
0.7
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
TA
(1)
(2)
(3)
Input transition rise or fall rate
20
VCC = 1.65 V to 2.3 V (3)
20
VCC = 2.3 V to 2.7 V (3)
20
Operating free-air temperature
mA
mA
9
(2)
VCC = 0.8 V to 1.65 V
Δt/Δv
V
–40
85
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).
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3
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
MIN TYP (1)
VCC
MAX
IOH = –100 μA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 μA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
IOL = 9 mA
2.3 V
0.6
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
VI = VCC or GND
0 to 2.7 V
5
μA
Ioff
VI or VO = 2.7 V
0
±10
μA
ICC
VI = VCC or GND,
0.8 V to 2.7 V
10
μA
CI
VI = VCC or GND
II
(1)
All inputs
IO = 0
2.5 V
2.5
pF
All typical values are at TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 0.8 V
TYP
fclock
Clock frequency
VCC = 1.2 V
± 0.1 V
MIN
50
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
MAX
VCC = 1.5 V
± 0.1 V
MIN
200
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
225
VCC = 2.5 V
± 0.2 V
MIN
250
275
CLK
2
1
1
1
1
PRE or CLR
low
5
1.5
1
1
1
Data
2.2
0.6
0.5
0.5
0.4
PRE or CLR
inactive
2.9
1.6
0.9
0.7
0.4
1.2
0.5
0.4
0.3
0.3
UNIT
MAX
MHz
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
PRE or CLR
4
VCC = 1.2 V
± 0.1 V
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
50
200
Q
10.3
1.7
3.7
1.2
2.5
1
1.2
1.7
0.8
1.2
Q
9.6
1
3.8
1
3
0.9
1.1
1.5
0.7
1.1
Q or Q
12.9
2
4.5
0.9
3.1
1.1
1.5
2.2
0.9
1.5
225
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MIN
TYP
VCC = 2.5 V
± 0.2 V
TYP
fmax
tpd
VCC = 0.8 V
MAX
250
MIN
UNIT
MAX
275
MHz
ns
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
VCC = 2.5 V
± 0.2 V
TYP MAX
250
CLK
PRE or CLR
UNIT
MIN MAX
275
ns
Q
1.5
1.9
2.4
1.4
1.8
Q
1.4
1.9
2.4
1.3
1.8
Q or Q
1.7
2.2
2.8
1.5
2.1
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
35
36
39
44
59
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UNIT
pF
5
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
VCC/2
Data Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
tPZL
tPLZ
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AUC1G74DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U74
Z
SN74AUC1G74DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(74, U74Q, U74R)
UZ
SN74AUC1G74DCURE4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U74R
SN74AUC1G74DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U74R
SN74AUC1G74RSER
ACTIVE
UQFN
RSE
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UP
SN74AUC1G74YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
UPN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of