SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
FEATURES
1
• Available in the Texas Instruments NanoFree™
Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• Ioff Supports Partial Power-Down-Mode
Operation
• Sub-1-V Operable
• Max tpd of 2.5 ns at 1.8 V
2
DBV PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
•
•
•
•
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
VCC
5
A
1
B
2
GND
3
5
4
VCC
GND
Y
3 4
B
2
A
1 5
VCC
Y
Y
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™
Reel of 3000
WCSP (DSBGA) – YZP (Pb-free)
SN74AUC1G86YZPR
_ _ _UH_
SOT (SOT-23) – DBV
Reel of 3000
SN74AUC1G86DBVR
U86_
SOT (SC-70) – DCK
Reel of 3000
SN74AUC1G86DCKR
UH_
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AUC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
EVEN-PARITY ELEMENT
2k
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
3.6
V
VI
Input voltage range (2)
–0.5
3.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
3.6
V
–0.5
VCC + 0.5
(2)
VO
Output voltage range
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
DBV package
206
DCK package
252
YZP package
(1)
(2)
(3)
2
V
°C/W
154
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUC1G86
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
0.8
2.7
UNIT
V
VCC
0.65 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
V
1.7
VCC = 0.8 V
0
0.35 × VCC
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V to 2.7 V
IOH
High-level output current
IOL
Low-level output current
0.7
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
mA
9
–40
20
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
MIN
TYP (1)
MAX
IOH = –100 µA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 µA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
2.3 V
0.6
IOL = 9 mA
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
VI = VCC or GND
0 to 2.7 V
±5
µA
Ioff
VI or VO = 2.7 V
0
±10
µA
ICC
VI = VCC or GND,
10
µA
Ci
VI = VCC or GND
II
(1)
A or B input
IO = 0
0.8 V to 2.7 V
2.5 V
2.5
pF
All typical values are at TA = 25°C.
Submit Documentation Feedback
Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUC1G86
3
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
A
tpd
B
VCC = 0.8 V
TO
(OUTPUT)
Y
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
TYP
MIN
MAX
5.5
0.8
3.8
0.5
5
0.8
3.8
0.5
VCC = 1.8 V
± 0.15 V
MIN MAX
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
2.6
0.4
1
1.7
0.3
1.3
2.6
0.4
1
1.7
0.3
1.2
UNIT
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
A
Y
B
VCC = 2.5 V
± 0.2 V
UNIT
MIN
TYP
MAX
MIN
MAX
0.8
1.5
2.6
0.7
2
0.8
1.5
2.6
0.7
2
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
4
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
16
16
16.5
17
18.5
Power dissipation capacitance
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UNIT
pF
Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUC1G86
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
S1
RL
From Output
Under Test
Open
S1
Open
2 × VCC
GND
GND
CL
(see Note A)
RL
LOAD CIRCUIT
VCC
CL
RL
VD
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kW
2 kW
2 kW
2 kW
2 kW
1 kW
500 W
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tW
tsu
VCC
Input
VCC/2
VCC/2
th
VCC
Data Input
VCC/2
VCC/2
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
VCC/2
Input
VCC/2
0V
tPLH
VOH
VCC/2
VOL
tPHL
VCC/2
0V
VCC
VCC/2
tPZH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VOH
Output
VCC/2
tPZL
tPHL
VCC/2
Output
VCC
Output
Control
VOL + VD
VOL
tPHZ
VCC/2
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W,
slew rate ³ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUC1G86
5
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74AUC1G86DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U86R
Samples
SN74AUC1G86DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UHR
Samples
SN74AUC1G86YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
UHN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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