SN74AUC2G04DCKR

SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 D D D D D D D D D DBV OR DCK PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.7 ns at 1.8 V Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1A GND 2A 1 6 2 5 3 4 1Y VCC 2Y YEP OR YZP PACKAGE (BOTTOM VIEW) 2A GND 1A 3 4 2 5 1 6 2Y VCC 1Y description/ordering information This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G04 performs the Boolean function Y = A. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION –40 C to 85 –40°C 85°C C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING‡ NanoStar – WCSP (DSBGA) 0.23-mm Large Bump – YEP Tape and reel SN74AUC2G04YEPR NanoFree – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Tape and reel SN74AUC2G04YZPR SOT (SOT-23) – DBV Tape and reel SN74AUC2G04DBVR U04_ SOT (SC-70) – DCK Tape and reel SN74AUC2G04DCKR UC_ _ _ _UC_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram (positive logic) 1A 2A 1 6 3 4 1Y 2Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V MIN MAX 0.8 2.7 UNIT V VCC 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 0.8 V V 1.7 0 0.35 × VCC VIL Low-level input voltage VI VO Input voltage 0 3.6 V Output voltage 0 VCC –0.7 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 0.8 V VCC = 1.1 V IOH High-level output current IOL Low-level output current ∆t/∆v V –3 VCC = 1.4 V VCC = 1.65 V –5 VCC = 2.3 V VCC = 0.8 V –9 mA –8 0.7 VCC = 1.1 V VCC = 1.4 V 3 VCC = 1.65 V VCC = 2.3 V 8 mA 5 9 Input transition rise or fall rate 20 ns/V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –0.7 mA VOH VOL II Ioff ICC Ci A inputs VCC 0.8 V to 2.7 V MIN MAX 0.8 V 0.55 1.1 V 0.8 1.4 V 1 IOH = –8 mA IOH = –9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.2 0.25 IOL = 3 mA IOL = 5 mA 1.1 V 0.3 1.4 V 0.4 IOL = 8 mA IOL = 9 mA 1.65 V 0.45 2.3 V 0.6 VI = VCC or GND VI or VO = 2.7 V VI = VCC or GND, VI = VCC or GND IO = 0 UNIT VCC–0.1 IOH = –3 mA IOH = –5 mA 0.8 V TYP† V 0 to 2.7 V ±5 µA 0 ±10 µA 0.8 V to 2.7 V 10 µA 2.5 V 2.1 pF † All typical values are at TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX A Y 5.4 0.9 3.1 0.7 2 0.6 1 1.7 0.5 1.2 tpd UNIT ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN TYP MAX MIN MAX 0.8 1.3 2 0.7 1.5 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V TYP VCC = 1.2 V TYP VCC = 1.5 V TYP VCC = 1.8 V TYP f = 10 MHz 12.5 12.5 12.5 12.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 2.5 V TYP 14 UNIT pF SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND CL RL 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input th VCC VCC/2 VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPLZ tPZL VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH tPLH VCC/2 VCC Output Control VCC/2 VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AUC2G04DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U04R SN74AUC2G04DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (UCF, UCR) SN74AUC2G04YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UCN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of