SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
FEATURES
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
•
•
•
Low Power Consumption, 10 μA at 1.8 V
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
DCU PACKAGE
(TOP VIEW)
1OE
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
1OE
1A
2Y
GND
1
2
3
8
7
6
4
5
YZP PACKAGE
(BOTTOM VIEW)
VCC
2OE
1Y
2A
GND
2Y
1A
1OE
4 5
3 6
2 7
1 8
2A
1Y
2OE
VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is high.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
0.23-mm Large Bump – YZP (Pb-free)
SN74AUC2G125YZPR
_ _ _UM_
SSOP – DCT
Reel of 3000
SN74AUC2G125DCTR
U25_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC2G125DCUR
U25_
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
1A
2
6
1Y
7
2OE
5
3
2A
2
2Y
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SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
3.6
V
VI
Input voltage range (2)
–0.5
3.6
V
–0.5
3.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±100
mA
Continuous current through VCC or GND
Package thermal impedance (3)
θJA
Tstg
(1)
(2)
(3)
DCT package
220
DCU package
227
YZP package
102
Storage temperature range
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
0.8
2.7
0.65 × VCC
VCC = 1.1 V to 1.95 V
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VI
Output voltage
IOH
High-level output current
IOL
Low-level output current
0
3.6
Active state
0
VCC
3-state
0
3.6
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
VCC = 0.8 V to 1.65 V
∆t/∆v
TA
(1)
(2)
(3)
Input transition rise or fall rate
V
V
mA
mA
9
(2)
20
VCC = 1.65 V to 1.95 V (3)
20
VCC = 2.3 V to 2.7 V (3)
15
Operating free-air temperature
V
0.7
Input voltage
VO
V
1.7
VCC = 0.8 V
Low-level input voltage
V
VCC
VCC = 2.3 V to 2.7 V
VIL
UNIT
–40
85
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).
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3
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
VCC
TYP (1)
MIN
MAX
IOH = –100 μA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 μA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
IOL = 9 mA
2.3 V
0.6
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
VI = VCC or GND
0 to 2.7 V
±5
μA
Ioff
VI or VO = 2.7 V
0
±10
μA
IOZ
VO = VCC or GND
2.7 V
±10
μA
ICC
VI = VCC or GND,
10
μA
Ci
VI = VCC or GND
2.5 V
2.5
pF
Co
VO = VCC or GND
2.5 V
5.5
pF
II
(1)
A or OE inputs
IO = 0
0.8 V to 2.7 V
All typical values are at TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A
Y
5.1
1
3.6
0.7
2.3
0.6
1
1.8
0.5
1.3
ns
ten
OE
Y
5.9
1.1
4.1
1
2.6
0.9
1.3
2
0.8
1.5
ns
tdis
OE
Y
6.6
2
4.8
1.5
3.5
1.8
2.6
3.7
1.4
2.9
ns
PARAMETER
UNIT
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
4
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
UNIT
MIN
TYP
MAX
MIN
MAX
Y
0.8
1.6
2.6
0.7
1.8
ns
Y
1.1
1.7
2.9
0.9
2.2
ns
Y
1.7
2.3
3.6
0.8
2
ns
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SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
16
16
16
17
18
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UNIT
pF
5
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
PARAMETER MEASUREMENT INFORMATION
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
S1
RL
From Output
Under Test
Open
S1
Open
2 × VCC
GND
GND
CL
(see Note A)
RL
LOAD CIRCUIT
VCC
CL
RL
VD
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kW
2 kW
2 kW
2 kW
2 kW
1 kW
500 W
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tW
tsu
VCC
Input
VCC/2
VCC/2
th
VCC
Data Input
VCC/2
VCC/2
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
VCC/2
Input
VCC/2
0V
tPLH
VOH
VCC/2
VOL
tPHL
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VOH
Output
VCC/2
tPZL
tPHL
VCC/2
Output
VCC
Output
Control
VOL + VD
VOL
tPHZ
VCC/2
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W,
slew rate ³ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AUC2G125DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U25
(R, Z)
SN74AUC2G125DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(U25Q, U25R)
SN74AUC2G125YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
UMN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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