SN74AUC2G80DCURG4

SN74AUC2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES540C – JANUARY 2004 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V • DCT PACKAGE (TOP VIEW) Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCU PACKAGE (TOP VIEW) 1CLK 1 8 VCC 1D 2 7 1Q 2Q 3 6 2D GND 4 5 2CLK 1CLK 1D 2Q GND 1 2 3 8 7 6 4 5 YZP PACKAGE (BOTTOM VIEW) VCC 1Q 2D 2CLK GND 2Q 1D 1CLK 4 5 3 6 2 7 1 8 2CLK 2D 1Q VCC See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoFree™ – WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump – YZP (Pb-free) SN74AUC2G80YZPR _ _ _UX_ SSOP – DCT Reel of 3000 SN74AUC2G80DCTR U80_ _ _ VSSOP – DCU Reel of 3000 SN74AUC2G80DCUR UX_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated SN74AUC2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES540C – JANUARY 2004 – REVISED JANUARY 2007 FUNCTION TABLE (EACH FLIP-FLOP) INPUTS CLK D OUTPUT Q ↑ H L ↑ L H L X Q0 LOGIC DIAGRAM (POSITIVE LOGIC) CLK C C C Q TG C C C C D TG TG TG C C C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 3.6 V –0.5 VCC + 0.5 range (2) VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range DCT package 220 DCU package 227 YZP package (1) (2) (3) 2 UNIT V °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74AUC2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES540C – JANUARY 2004 – REVISED JANUARY 2007 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 UNIT V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.7 VCC = 0.8 V 0 0.35 × VCC VIL Low-level input voltage VCC = 1.1 V to 1.95 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.7 V IOH High-level output current IOL Low-level output current 0.7 VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V mA mA 9 –40 20 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC MIN TYP (1) MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA UNIT VCC – 0.1 0.55 V 0.2 0.25 V 2.3 V 0.6 VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±5 µA ICC VI = VCC or GND, 10 µA Ci VI = VCC or GND II (1) D or CLK inputs IO = 0 0.8 V to 2.7 V 2.5 V 2.5 pF All typical values are at TA = 25°C. Submit Documentation Feedback 3 SN74AUC2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES540C – JANUARY 2004 – REVISED JANUARY 2007 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V VCC = 0.8 V TYP fclock Clock frequency 50 tw Pulse duration, CLK high or low 2.4 tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX VCC = 1.5 V ± 0.1 V MIN VCC = 1.8 V ± 0.15 V MAX 200 MIN MAX 225 VCC = 2.5 V ± 0.2 V MIN UNIT MAX 250 275 MHz 1 1 1 1 ns 1 0.8 0.6 0.6 0.5 ns 0 0 0.1 0.1 0.5 ns Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 0.8 V fmax tpd CLK Q VCC = 1.2 V ± 0.1 V TYP MIN 50 200 5 1 MAX VCC = 1.5 V ± 0.1 V MIN VCC = 1.8 V ± 0.15 V MAX MIN 225 3.9 0.8 TYP VCC = 2.5 V ± 0.2 V MAX 250 2.5 MIN 275 0.3 1 1.9 UNIT MAX MHz 0.3 1.3 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) CLK Q fmax VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V TYP MAX 1.5 2.4 250 tpd 0.8 MIN UNIT MAX 275 ns 0.6 1.8 ns Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Data Cpd Power dissipation capacitance CLK Total 4 fclock = 10 MHz VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP 16.9 17.2 18.6 21.4 29.5 1.1 1.1 1.2 1.4 2.5 18 18.3 19.8 22.8 32 Submit Documentation Feedback UNIT pF SN74AUC2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES540C – JANUARY 2004 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tW tsu VCC Input VCC/2 VCC/2 th VCC Data Input VCC/2 VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPLH VOH VCC/2 VOL tPHL VCC/2 tPLZ VCC VCC/2 tPZH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL tPHL VCC/2 Output VCC Output Control VOL + VD VOL tPHZ VCC/2 VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, slew rate ³ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AUC2G80DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U80 (R, Z) Samples SN74AUC2G80DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (U80Q, U80R) Samples SN74AUC2G80YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UXN Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of