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SN74AUP1G79
SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
3 Description
•
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assures a very-low
static and dynamic power consumption across the
entire VCC range of 0.8 V to 3.6 V, thus resulting in an
increased battery life. The AUP devices also maintain
excellent signal integrity.
•
•
•
•
•
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Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption:
ICC = 0.9 µA Maximum
Low Dynamic-Power Consumption:
Cpd = 3 pF Typical at 3.3 V
Low Input Capacitance:
Ci = 1.5 pF Typical
Low Noise: Overshoot and Undershoot
< 10% of VCC
Ioff Supports Partial Power-Down-Mode Operation
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
tpd = 4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
2 Applications
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Barcode Scanner
Cable Solutions
E-Book
Embedded PC
Field Transmitter: Temperature or Pressure
Sensor
Fingerprint Biometrics
HVAC: Heating, Ventilating, and Air Conditioning
Network-Attached Storage (NAS)
Server Motherboard and PSU
Software Defined Radio (SDR)
TV: High-Definition (HDTV), LCD, and Digital
Video Communications System
Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
The SN74AUP1G79 is a single positive-edgetriggered D-type flip-flop. When data at the data (D)
input meets the setup-time requirement, the data is
transferred to the Q output on the positive-going edge
of the clock pulse. Clock triggering occurs at a
voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
The SN74AUP1G79 device is fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs when the device is
powered down. This inhibits current backflow into the
device which prevents damage to the device.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G79DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUP1G79DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1G79DRL
SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74AUP1G79DRY
SON (6)
1.45 mm × 1.00 mm
SN74AUP1G79DSF
SON (6)
1.00 mm × 1.00 mm
SN74AUP1G79DPW
X2SON (5)
0.80 mm x 0.80 mm
SN74AUP1G79YFP
DSBGA (6)
1.16 mm × 0.76 mm
SN74AUP1G79YZP
DSBGA (5)
1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Power Consumption and Performance
Switching Characteristics
at 25 MHz†
3.5
3
Voltage − V
1
2.5
Input
2
1.5
1
Output
0.5
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G79
SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: TA = 25°C ........................ 6
Electrical Characteristics: TA = –40°C to 85°C ......... 7
Timing Requirements ................................................ 8
Switching Characteristics: CL = 5 pF ........................ 9
Switching Characteristics: CL = 10 pF ...................... 9
Switching Characteristics: CL = 15 pF .................. 10
Switching Characteristics: CL = 30 pF .................. 11
Operating Characteristics...................................... 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 13
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Width.............................................................. 13
7.2 Enable and Disable Times ...................................... 14
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
16
Applications, Implementation, and Layout ....... 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2015) to Revision I
Page
•
Added DPW (X2SON) package.............................................................................................................................................. 1
•
Added Maximum junction temperature, TJ in Absolute Maximum Ratings ............................................................................ 4
•
Changed values in the Thermal Information table to align with JEDEC standards. .............................................................. 5
•
Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), Over-voltage Tolerant Inputs ........................................................................................................................................ 15
•
Added Receiving Notification of Documentation Updates and Community Resources ....................................................... 20
Changes from Revision G (May 2010) to Revision H
Page
•
Updated document to the new TI data sheet format .............................................................................................................. 1
•
Removed Ordering Information table .................................................................................................................................... 1
•
Added Device Information table ............................................................................................................................................ 1
•
Added Typical Characteristics section.................................................................................................................................. 12
2
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SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
D
1
CLK
2
GND
DCK Package
5-Pin SC70
Top View
VCC
5
3
D
1
CLK
2
GND
3
DRL Package
5-Pin SOT-5X3
Top View
1
CLK
2
GND
3
5
VCC
VCC
Q
Q
4
DSF Package
6-Pin SON
Top View
1
6
VCC
CLK
2
5
NC
GND
3
4
Q
YFP Package
6-Pin DSBGA
Bottom View
A
Q
D
CLK
GND
D
B
4
DPW Package
5-Pin X2SON
Top View
DRY Package
6-Pin SON
Top View
C
VCC
Q
4
D
5
1
2
GND
Q
CLK
N.C.
D
VCC
D
1
6
VCC
CLK
2
5
NC
GND
3
4
Q
YZP Package
5-Pin DSBGA
Bottom View
Not to scale
1
2
C
GND
Q
B
CLK
A
D
VCC
Not to scale
Pin Functions
PIN
DBV, DCK,
DRL, DPW
DRY,
DSF
YZP
YFP
CLK
2
2
B1
B1
D
1
1
A1
GND
3
3
C1
NC
—
5
—
B2
Q
4
4
C2
VCC
5
6
A2
NAME
I/O
DESCRIPTION
I
Positive-Edge-Triggered Clock input
A1
I
Data Input
C1
—
Ground pin
—
No Connect
C2
O
Q output
A2
—
Positive supply
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SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
VI
Input voltage
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
TJ
Maximum junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
6.3 Recommended Operating Conditions
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
UNIT
0.8
3.6
V
VCC
VCC = 1.1 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.6
VCC = 3 V to 3.6 V
2
VCC = 0.8 V
VIL
Low-level input voltage
Input voltage
VO
Output voltage
IOH
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.9
(1)
VI
High-level output current
Low-level output current
3.6
0
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
V
0
VCC = 3 V
IOL
V
µA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to assure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74AUP1G79
THERMAL METRIC (1)
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT-5X3)
DRY
(SON)
DSF
(SON)
DPW
(X2SON)
YFP
(DSBGA)
YZP
(DSBGA)
UNIT
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
5 PINS
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal
resistance
267.2
284.1
294.1
341.1
377.1
489.2
125.4
146.2
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
191.9
208.5
132.5
233.1
187.7
226.3
1.9
1.4
°C/W
RθJB
Junction-to-board thermal
resistance
101.1
103.1
143.4
206.7
236.6
352.9
37.2
39.3
°C/W
ψJT
Junction-to-top characterization
parameter
83.0
76.6
14.5
63.4
29.0
38.2
0.5
0.7
°C/W
ψJB
Junction-to-board
characterization parameter
100.8
102.3
143.9
206.7
236.3
352.1
37.5
39.8
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
150.8
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: TA = 25°C
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
IOH = –1.7 mA
1.4 V
1.11
IOH = –1.9 mA
1.65 V
1.32
IOH = –2.3 mA
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
MAX
1.9
2.72
2.6
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
IOL = 1.9 mA
1.65 V
0.31
0.1
0.31
2.3 V
IOL = 2.7 mA
VI = GND to 3.6 V
V
0.44
0.31
3V
IOL = 4 mA
UNIT
V
2.05
0.8 V to 3.6 V
IOL = 3.1 mA
II
TYP
IOL = 20 µA
IOL = 2.3 mA
D or CLK
input
MIN
0.44
0 V to 3.6 V
0.1
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
µA
ICC
VI = GND or VCC to 3.6 V,
IO = 0
0.8 V to 3.6 V
0.5
µA
IO = 0
3.3 V
40
µA
ΔICC
VI = VCC – 0.6 V,
Ci
VI = VCC or GND
Co
VO = GND
(1)
6
(1)
0V
1.5
3.6 V
1.5
0V
3
pF
pF
One-input switching
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6.6 Electrical Characteristics: TA = –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.03
IOH = –1.9 mA
1.65 V
1.3
IOH = –2.3 mA
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
1.85
2.67
2.55
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.37
IOL = 1.9 mA
1.65 V
0.35
2.3 V
IOL = 2.7 mA
3V
IOL = 4 mA
VI = GND to 3.6 V
UNIT
V
1.97
0.8 V to 3.6 V
IOL = 3.1 mA
II
MAX
IOL = 20 µA
IOL = 2.3 mA
D or CLK
input
MIN
0.33
V
0.45
0.33
0.45
0 V to 3.6 V
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.6
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.6
µA
ICC
VI = GND or VCC to 3.6 V,
IO = 0
0.8 V to 3.6 V
0.9
µA
IO = 0
3.3 V
50
µA
ΔICC
(1)
VI = VCC – 0.6 V,
(1)
One-input switching
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6.7 Timing Requirements
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
VCC
MIN
TYP (1)
0.8 V
fclock
Clock frequency
Pulse duration, CLK high or low
Data high
tsu
Setup time before
CLK↑
Data low
th
(1)
8
Hold time, data after CLK↑
UNIT
20
1.2 V ± 0.1 V
80
1.5 V ± 0.1 V
100
1.8 V ± 0.15 V
140
2.5 V ± 0.2 V
210
3.3 V ± 0.3 V
tw
MAX
MHz
260
0.8 V
4.8
1.2 V ± 0.1 V
2.2
1.5 V ± 0.1 V
1.5
1.8 V ± 0.15 V
1.6
2.5 V ± 0.2 V
1.7
3.3 V ± 0.3 V
1.9
0.8 V
4.2
1.2 V ± 0.1 V
1.4
1.5 V ± 0.1 V
1
1.8 V ± 0.15 V
0.9
2.5 V ± 0.2 V
0.7
3.3 V ± 0.3 V
0.6
0.8 V
5.3
1.2 V ± 0.1 V
1.8
1.5 V ± 0.1 V
1.2
1.8 V ± 0.15 V
1.1
2.5 V ± 0.2 V
1
3.3 V ± 0.3 V
1
0.8 V
0
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
ns
2.9
3.5
ns
0
ns
TA = 25°C
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6.8 Switching Characteristics: CL = 5 pF
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TA = –40°C to +85°C
199
220
250
230
TA = 25°C
TA = –40°C to +85°C
240
280
250
TA = 25°C
TA = –40°C to +85°C
280
260
TA = 25°C
15.9
TA = 25°C
3.7
TA = –40°C to +85°C
2.6
TA = 25°C
TA = –40°C to +85°C
MHz
271
TA = 25°C
TA = –40°C to +85°C
UNIT
93
TA = 25°C
TA = –40°C to +85°C
MAX
90
TA = 25°C
TA = –40°C to +85°C
TYP
3
6.9
4.8
2
TA = 25°C
2.4
TA = –40°C to +85°C
1.5
TA = 25°C
1.8
TA = –40°C to +85°C
1.1
TA = 25°C
1.5
TA = –40°C to +85°C
0.9
11
13.1
7.6
8.8
3.8
6.1
ns
7.1
2.7
4.4
2.1
3.6
5
4
6.9 Switching Characteristics: CL = 10 pF
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TA = –40°C to +85°C
147
160
189
200
TA = 25°C
TA = –40°C to +85°C
180
260
250
TA = 25°C
TA = –40°C to +85°C
280
260
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MHz
240
TA = 25°C
TA = –40°C to +85°C
UNIT
62
TA = 25°C
TA = –40°C to +85°C
MAX
50
TA = 25°C
TA = –40°C to +85°C
TYP
9
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SCES592I – JULY 2004 – REVISED SEPTEMBER 2017
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Switching Characteristics: CL = 10 pF (continued)
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TYP
TA = 25°C
4.3
7.8
TA = –40°C to +85°C
3.2
TA = 25°C
3.5
TA = –40°C to +85°C
2.5
TA = 25°C
2.8
TA = –40°C to +85°C
1.9
TA = 25°C
2.2
TA = –40°C to +85°C
1.5
TA = 25°C
1.8
TA = –40°C to +85°C
1.3
TA = 25°C
MAX
UNIT
18
12.3
14.4
5.5
8.4
9.8
4.4
6.8
ns
8
3.2
5
5.7
2.6
4.1
4.5
6.10 Switching Characteristics: CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
10
MIN
TA = 25°C
MAX
UNIT
48
TA = –40°C to +85°C
30
TA = 25°C
112
TA = –40°C to +85°C
120
TA = 25°C
151
TA = –40°C to +85°C
160
TA = 25°C
MHz
194
TA = –40°C to +85°C
220
TA = 25°C
248
TA = –40°C to +85°C
250
TA = 25°C
280
TA = –40°C to +85°C
260
TA = 25°C
20.3
TA = 25°C
5
TA = –40°C to +85°C
3.9
TA = 25°C
4.1
TA = –40°C to +85°C
3.1
TA = 25°C
3.3
TA = –40°C to +85°C
2.4
TA = 25°C
2.6
TA = –40°C to +85°C
1.9
TA = 25°C
2.2
TA = –40°C to +85°C
1.6
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TYP
8.7
13.6
15.6
6.3
9.3
10.7
4
7.6
ns
8.7
3.6
5.5
6.3
3
4.5
5
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6.11 Switching Characteristics: CL = 30 pF
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TA = 25°C
VCC = 0.8 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.5 V ± 0.1 V
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MAX
UNIT
20
TA = 25°C
72
TA = –40°C to +85°C
80
TA = 25°C
100
TA = –40°C to +85°C
100
TA = 25°C
MHz
127
TA = –40°C to +85°C
140
TA = 25°C
185
TA = –40°C to +85°C
210
TA = 25°C
266
TA = –40°C to +85°C
260
TA = 25°C
VCC = 1.2 V ± 0.1 V
TYP
24
TA = –40°C to +85°C
VCC = 1.2 V ± 0.1 V
tpd
MIN
27.2
TA = 25°C
7
TA = –40°C to +85°C
5.9
TA = 25°C
5.7
TA = –40°C to +85°C
4.6
TA = 25°C
4.7
TA = –40°C to +85°C
3.8
TA = 25°C
3.7
TA = –40°C to +85°C
2.9
TA = 25°C
3.2
TA = –40°C to +85°C
2.6
11.5
17.3
8.3
11.8
24
15.9
6.7
9.6
ns
13
4.9
7
4.1
5.8
9
7.2
6.12 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
2.5
1.2 V ± 0.1 V
2.5
1.5 V ± 0.1 V
2.5
1.8 V ± 0.15 V
2.5
2.5 V ± 0.2 V
3
3.3 V ± 0.3 V
3
UNIT
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6.13 Typical Characteristics
6
18
TPD in ns
16
5
14
4
TPD (ns)
TPD (ns)
12
10
8
3
2
6
4
1
2
TPD in ns
0
0
1
2
VCC (V)
3
4
0
-50
D001
Figure 1. TPD vs VCC
12
0
50
Temperature (qC)
100
150
D001
Figure 2. TPD vs Temperature
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7 Parameter Measurement Information
7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
From Output
Under Test
CL
(see Note A)
1 MW
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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7.2 Enable and Disable Times
2 × VCC
S1
5 kW
From Output
Under Test
GND
CL
(see Note A)
5 kW
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
VD
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL + VD
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
14
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8 Detailed Description
8.1 Overview
The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. Data at the input (D) is transferred to the
output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the
clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows
for data at the input to be changed without affecting the level at the output, following the hold-time interval.
8.2 Functional Block Diagram
CLK
CLK
Q
Q
D
D
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all
times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics: TA = 25°C. The worst case resistance is calculated with the
maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given
in the Electrical Characteristics: TA = 25°C, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
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Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
-IIK
Output
-IOK
GND
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics: TA = 25°C.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1G79 device.
Table 1. Function Table
INPUTS
16
CLK
D
OUTPUT
Q
↑
H
H
↑
L
L
L or H
X
Q0
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9 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A rotary quadrature encoder is a simple, infinitely-turning knob that outputs two out-of-phase square waves as it
is turned and is often used in electronics as a method of human interface. One signal will lead the other in phase
depending on which direction the knob is turned. The SN74AUP1G79 can be used to determine which direction
the knob is being turned without the need for a microcontroller or other complex monitoring system by connecting
the outputs of the knob to the D and CLK inputs of the SN74AUP1G79 as shown in Figure 7. It is important to
note that the CLK input will control when the direction signal changes, as shown in Figure 8.
9.2 Typical Application
0.8-3.6V
SN74AUP1G79
QINA
Quadrature
Encoder
QINB
1
D
VCC
5
0.1 F
2
CLK
3
GND
Q
4
DIR
Figure 7. Typical Application Diagram
QINA
tpd
tpd
QINB
DIR
Figure 8. Timing Diagram for Quadrature Encoder Application
9.2.1 Design Requirements
The SN74AUP1G79 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specifications. See Δt/ΔV in Recommended Operating Conditions.
– Specified high and low levels. See VIH and VIL in Recommended Operating Conditions.
– Inputs are overvoltage tolerant, which allows them to go as high as 3.6 V at any valid VCC
2. Recommended output conditions
– Load currents must not exceed 20 mA on the output and 50 mA total for the part
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Typical Application (continued)
9.2.3 Application Curves
Switching Characteristics
at 25 MHz†
3.5
Voltage − V
3
2.5
Input
2
1.5
1
Output
0.5
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 9. AUP – The Lowest-Power Family
18
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Figure 10. Excellent Signal Integrity
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. A 0.1-µF bypass capacitor is recommended to be connected from
the VCC terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple
bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The
bypass capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 11 shows progressively better techniques of rounding corners. Only the
last example (BEST) maintains constant trace width and minimizes reflections.
An example layout is given in Figure 12 for the DPW (X2SON-5) package. This example layout includes a 0402
(metric) capacitor and uses the measurements found in the example board layout appended to this end of this
datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or it can be left out of the layout
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 11. Trace Example
4 mil
0402
0.1 …F
Bypass Capacitor
8 mil
8 mil
8 mil
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK, TYP
Figure 12. Example Layout With DPW (X2SON-5) Package
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74AUP1G79DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H79R
Samples
SN74AUP1G79DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H79R
Samples
SN74AUP1G79DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H79R
Samples
SN74AUP1G79DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HWF, HWK, HWO, HW
R)
Samples
SN74AUP1G79DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HWO, HWR)
Samples
SN74AUP1G79DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
9N
Samples
SN74AUP1G79DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HWR
Samples
SN74AUP1G79DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HW
Samples
SN74AUP1G79DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HW
Samples
SN74AUP1G79YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
HWN
Samples
SN74AUP1G79YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
HWN
Samples
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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