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SN74AUP1T34
SCES841F – JUNE 2012 – REVISED APRIL 2018
SN74AUP1T34 1-Bit Unidirectional Voltage-Level Translator
1 Features
3 Description
•
•
The SN74AUP1T34 device is a 1-bit noninverting
translator that uses two separate configurable powersupply rails. It is a uni-directional translator from A to
B. The A port is designed to track VCCA. VCCA accepts
supply voltages from 0.9 V to 3.6 V. The B port is
designed to track VCCB. VCCB accepts supply voltages
from 0.9 V to 3.6 V. This allows for low-voltage
translation between 1-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V,
and 3.3-V voltage nodes. The SN74AUP1T34 is also
fully specified for partial-power-down applications
using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the
device when it is powered down.
1
•
•
•
•
•
•
•
•
Wide Operating VCC Range of 0.9 V to 3.6 V
Balanced Propagation Delays: tPLH = tPHL (1.8-V to
3.3-V Translation Typical)
Low Static-Power Consumption: Maximum of 5-µA
ICC
±6-mA Output Drive at 3 V
Ioff Supports Partial Power-Down-Mode Operation
VCC Isolation Feature – If VCCA Input Is at GND,
B Port Is in the High-Impedance state
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at Input
ESD Protection Exceeds JESD 22
5000-V Human-Body Model (A114-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
The VCC isolation feature ensures that if VCCA input
is at GND, the B port is in the high-impedance state.
If VCCB input is at GND, any input to the A side does
not cause the leakage current even floating.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Enterprise
Industrial
Personal Electronics
Telecommunications
PACKAGE
BODY SIZE (NOM)
SN74AUP1T34DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1T34DRY
SON (6)
1.45 mm × 1.00 mm
SN74AUP1T34DSF
SON (6)
1.00 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Example Application
Bluetooth Module
Applications
Processor
SN74AUP1T34
Control Output
WiFi Module
To Multiple
Loads
Baseband Module
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1T34
SCES841F – JUNE 2012 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
8
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: DC ................................... 7
Electrical Characteristics: AC ................................... 8
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
13.1 Package Option Addendum .................................. 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2016) to Revision F
Page
•
Added operating junction temperature to Absolute Maximum Ratings table ........................................................................ 5
•
Updated Recommended Operating Conditions table ............................................................................................................ 6
•
Updated the VCCB value for the parameter 'high-level input voltage' in the Recommended Operating Conditions table ...... 6
•
Updated the VCCB value for the parameter 'low-level input voltage' in the Recommended Operating Conditions table ........ 6
•
Added Electrical Characteristics: DC table ............................................................................................................................ 7
Changes from Revision D (April 2016) to Revision E
•
Page
Changed pin A number From: 3 To: 2 and GND From: 2 To: 3 for the SC70 package in the Pin Configuration and
Functions section ................................................................................................................................................................... 4
Changes from Revision C (May 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table ..................................................................................................................................... 1
Changes from Revision B (July 2012) to Revision C
Page
•
Added Feature: VCC Isolation Feature – If VCCA Input Is at GND, B Port Is in the High-Impedance state. .......................... 1
•
Updated Pin Functions table. ................................................................................................................................................. 4
•
Deleted IOZ PARAMETER from RECOMMENDED OPERATION CONDITIONS. ................................................................. 6
•
Added VMI and VMO equations to Wavefrom 1 graphic......................................................................................................... 10
•
Added FUNCTION TABLE. .................................................................................................................................................. 12
2
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Changes from Revision A (June 2012) to Revision B
•
Page
Removed Feature: Output Enable Feature Allows User to Disable Outputs to Reduce Power Consumption. .................... 1
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5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
VCCA
1
A
2
GND
3
DRY or DSF Package
6-Pin SON
Top Through View
5
V
4
CCB
V
B
1
6
V
A
2
5
NC
GND
3
4
B
CCA
CCB
Pin Functions
PIN
NAME
I/O
DESCRIPTION
SC70
SON
A
2
2
I
Input Port
B
4
4
O
Output Port
GND
3
3
—
Ground
VCCA
1
1
—
Input Port DC Power Supply
VCCB
5
6
—
Output Port DC Power Supply
NC
—
5
—
No Connect. Leave floating.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCCA and VCCB
Input voltage, VI
Voltage applied to any output in the high-impedance or power-off state, VO
Voltage applied to any output in the high or low state, VO
MIN
MAX
–0.3
4
–0.5
4.6
–0.5
4.6
–0.5
4.6
–0.5
4.6
–0.5
4.6
–0.5
4.6
–0.5
4.6
UNIT
V
V
V
V
Input clamp current, IIK
VI < 0 V
–50
mA
Output clamp current, IOK
VO < 0 V
–50
mA
±50
mA
±100
mA
150
°C
150
°C
Continuous output current, IO
Continuous current through VCCA or GND
Storage temperature, Tstg
–65
Operating junction temperature, TJ
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
5000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
0.9
3.6
V
VCCB
Supply voltage
0.9
3.6
V
VIH
High-level input voltage
VIH
Low-level input voltage
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
VCCA = 0.9 V to 1.95 V
VCCB = 0.9 V to 3.6 V
0.65 ×
VCCA
VCCA = 2.3 V to 2.7 V
VCCB = 0.9 V to 3.6 V
1.6
VCCA = 3 V to 3.6 V
VCCB = 0.9 V to 3.6 V
2
VCCA = 0.9 V
VCCB = 0.9 V to 3.6 V
0.3 ×
VCCA
VCCA = 1 V to 1.95 V
VCCB = 0.9 V to 3.6 V
0.35 ×
VCCA
VCCA = 2.3 V to 2.7 V
VCCB = 0.9 V to 3.6 V
0.7
VCCA = 3 V to 3.6 V
VCCB = 0.9 V to 3.6 V
0.9
VCCA = 3 V to 3.6 V
VCCB = 0.9 V to 3.6 V
200
ns/V
85
°C
V
–40
V
6.4 Thermal Information
SN74AUP1T34
THERMAL METRIC (1)
DCK (SC70)
DRY (SON)
DSF (SON)
UNIT
5 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
300.8
338.5
367.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
141.3
240.4
188.8
°C/W
RθJB
Junction-to-board thermal resistance
77.3
224.6
274.6
°C/W
ψJT
Junction-to-top characterization parameter
12.6
86.8
24.1
°C/W
ψJB
Junction-to-board characterization parameter
76.5
221.4
273.1
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: DC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output
voltage
Low-level output
voltage
TEST CONDITIONS
VI = VIH
VI = VIL
VCCA
VCCB
MIN
IOH = –100 µA
0.9 V to 3.6 V
0.9 V to 3.6 V
VCCB – 0.2
IOH = –0.25 mA
0.9 V to 1 V
0.9 V to 1 V
0.75 × VCCB
MAX
IOH = –1.5 mA
1.2 V
1.2 V
1
IOH = –2 mA
1.65 V
1.65 V
1.32
IOH = –3 mA
2.3 V
2.3 V
1.9
IOH = –6 mA
3V
3V
2.72
IOL = 100 µA
0.9 V to 3.6 V
0.9 V to 3.6 V
IOL = 0.25 mA
0.9 V to 1 V
0.9 V to 1 V
IOL = 1.5 mA
1.2 V
1.2 V
0.3 × VCCB
IOL = 2 mA
1.65 V
1.65 V
0.31
IOL = 3 mA
2.3 V
2.3 V
0.31
IOL = 6 mA
3V
3V
0.31
V
0.1
0.1
II
Input leakage
current
VI = VCCA or GND
0.9 V to 3.6 V
0.9 V to 3.6 V
±1
Ioff
Off-state current
A or B port:
VI or VO = 0 to 3.6 V
0V
0 V to 3.6 V
±5
0 V to 3.6 V
0V
±5
0.9 V to 3.6 V
0.9 V to 3.6 V
5
0.9 V to 3.6 V
VCCA
2
0V
0 V to 3.6 V
1
0 V to 3.6 V
0V
1
0.9 V to 3.6 V
0.9 V to 3.6 V
5
0.9 V to 3.6 V
VCCA
2
0V
0 V to 3.6 V
1
0 V to 3.6 V
0V
1
0.9 V to 3.6 V
0.9 V to 3.6 V
3.3 V
0V
ICCA
ICCB
VCCA supply
current
VCCB supply
current
VI = VCCI or GND,
IO = 0 mA
VI = VCCI or GND,
IO = 0 mA
VI = VCCI or GND,
IO = 0 mA
ICCA +
ICCB
Combined supply
current
CI
Input capacitance VI = 3.3 V or GND
CI/O
Input-to-output
internal
capacitance
A or B port:
VO = 3.3 V or GND
UNIT
V
µA
µA
µA
µA
5.2
µA
3.3 V
4
pF
3.3 V
7
pF
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6.6 Electrical Characteristics: AC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
0.9 V
CL = 5 pF
CL = 5 pF
tPLH/tPHL
Propagation delay time
low-to-high output / high-to-low output
CL = 5 pF
CL = 5 pF
CL = 5 pF
0.9 V
1.2 V
1.65 V
2.3 V
3V
MIN
TYP
1.2 V
18
1.65 V
16.2
2.3 V
16.3
3V
16.8
0.9 V
42.5
1.2 V
24.9
1.65 V
23.2
2.3 V
22.6
3V
22.5
0.9 V
40
1.2 V
10.7
1.65 V
8.84
2.3 V
8.08
3V
7.88
0.9 V
41.3
1.2 V
8.02
1.65 V
5.73
2.3 V
4.92
3V
4.2
0.9 V
42.5
1.2 V
7.61
1.65 V
4.5
2.3 V
3.65
3V
CL = 10 pF
0.9 V
28.9
1.2 V
19.8
1.65 V
17.9
3V
tPLH/tPHL
Propagation delay time
low-to-high output / high-to-low output
CL = 10 pF
CL = 10 pF
CL = 10 pF
8
1.2 V
1.65 V
2.3 V
3V
ns
18
18.5
0.9 V
43.22
1.2 V
12.33
1.65 V
9.57
2.3 V
8.81
3V
8.61
0.9 V
40.44
1.2 V
9.21
1.65 V
6.57
2.3 V
5.5
3V
4.73
0.9 V
41.56
1.2 V
8.3
1.65 V
5.54
2.3 V
4.42
3V
4.01
0.9 V
42.81
1.2 V
7.87
1.65 V
4.55
2.3 V
3.8
3V
3.36
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UNIT
3.39
0.9 V
2.3 V
CL = 10 pF
MAX
25
ns
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Electrical Characteristics: AC (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CL = 15 pF
CL = 15 pF
tPLH/tPHL
Propagation delay time
low-to-high output / high-to-low output
CL = 15 pF
CL = 15 pF
CL = 15 pF
VCCA
0.9 V
1.2 V
1.65 V
2.3 V
3V
VCCB
MIN
TYP
0.9 V
30.6
1.2 V
21.6
1.65 V
19.6
2.3 V
19.7
3V
20.3
0.9 V
43.87
1.2 V
12.98
1.65 V
10.3
2.3 V
9.54
3V
9.34
0.9 V
40.78
1.2 V
9.59
1.65 V
6.95
2.3 V
5.87
3V
5.07
0.9 V
41.79
1.2 V
8.55
1.65 V
5.8
2.3 V
4.68
3V
4.27
0.9 V
43.09
1.2 V
8.16
1.65 V
4.84
2.3 V
4.09
3V
CL = 30 pF
0.9 V
32.1
1.2 V
21.3
1.65 V
18.7
3V
tPLH/tPHL
Propagation delay time
low-to-high output / high-to-low output
CL = 30 pF
CL = 30 pF
CL = 30 pF
1.2 V
1.65 V
2.3 V
3V
18
45.65
1.2 V
14.76
1.65 V
12.37
2.3 V
11.61
3V
11.41
0.9 V
41.72
1.2 V
10.65
1.65 V
8.01
2.3 V
6.94
3V
5.99
0.9 V
42.44
1.2 V
9.26
1.65 V
6.51
2.3 V
5.39
3V
4.97
0.9 V
43.69
1.2 V
8.8
1.65 V
5.48
2.3 V
4.72
3V
4.28
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ns
18.3
0.9 V
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UNIT
3.65
0.9 V
2.3 V
CL = 30 pF
MAX
ns
9
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VIH
Vm
Input (An)
Vm
0V
tPLH
tPLH
Vm
Output(Bn)
VOH
Vm
VOL
VMI =VIH/2; VMO= VCCB/2
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 1. Waveform 1 – Propagation Delays
10
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6.7 Typical Characteristics
0.600
Low Level Output Voltage [V]
0.500
0.400
0.300
0.200
VCCB = 1.0V
VCCB = 1.2V
VCCB = 1.5V
0.100
VCCB = 1.8V
VCCB = 2.5V
VCCB = 3.3V
0.000
0.00
5.00
10.00
15.00
20.00
25.00
30.00
Low Level Output Current [mA] with VIL = 0V
C001
Figure 2. Low Level Output Voltage vs Low Level Output Current
7 Parameter Measurement Information
VCC
Pulse
Generator
DUT
CL
RL
TEST
tPLH, tPHL
CL = 5 pF, 10 pF, 15 pF, 30 pF or equivalent (includes probe and jig capacitance)
RL = 1 MΩ or equivalent
ZOUT of pulse generator = 50 Ω
Figure 3. AC (Propagation Delay) Test Circuit
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8 Detailed Description
8.1 Overview
The SN74AUP1T34 is a unidirectional, single-bit, dual-supply, noninverting voltage-level translator. Pin A, which
is referenced to VCCA, receives the signal that is to be level translated. Pin B, which is referenced to VCCB,
transmits the level translated signal. Both supply pins VCCA and VCCB support a voltage range from 0.9 V to
3.6 V.
8.2 Functional Block Diagram
VCCA
VCCB
2
4
A
B
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design
Both VCCA and VCCB can be supplied at any voltage from 0.9 V to 3.6 V, making the device suitable for translating
between any of the voltage nodes (1 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Partial-Power-Down Mode Operation
Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74AUP1T34 when it is
powered down. This can occur in applications where subsections of a system are powered down (partial-powerdown) to reduce power consumption.
8.3.3 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports A and B are set
to a high-impedance state, preventing false logic levels from being presented to either bus.
8.3.4 Input Hysteresis
Input hysteresis allows the input to support slew rates as slow as 200 ns/V, improving switching noise immunity.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1T34.
Table 1. Function Table
12
INPUT
OUTPUT
A PORT
B PORT
L
L
H
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AUP1T34 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another.
9.2 Typical Application
1.0 V
3.3 V
1.0 µF
1.0 µF
0.1 µF
VCCA
VDD (1.0 V)
1.0V Controller
0.1 µF
VCCB
VDD (3.3 V)
SN74AUP1T34
Signal
A
GND
3.3V System
B
Signal
GND
GND
a
Figure 4. Typical Application Example
9.2.1 Design Requirements
Table 2 lists the design requirements of the SN74AUP1T34.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage Range
0.9 V to 3.6 V
Output Voltage Range
0.9 V to 3.6 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AUP1T34 device to determine the input
voltage range. For a valid logic-high, the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AUP1T34 device is driving to determine the output
voltage range.
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9.2.3 Application Curve
Figure 5. 10-MHz Up Translation (0.9 V to 3.6 V)
14
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10 Power Supply Recommendations
Connect ground before applying either VCCA or VCCB. There is no specific power sequence requirement for the
SN74AUP1T34. VCCA or VCCB may be powered up first, and VCCA or VCCB may be powered down first.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines is
recommended.
• Bypass capacitors must be used on power supplies.
• Short trace lengths must be used to avoid excessive loading.
• Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
Bypass Capacitor
Bypass Capacitor
From Source
1
VCCA
2
A
3
GND
VCCB
5
B
4
To Destination
SN74AUP1T34DCK
(Top View)
Figure 6. Example Layout
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Product Folder Links: SN74AUP1T34
15
SN74AUP1T34
SCES841F – JUNE 2012 – REVISED APRIL 2018
www.ti.com
12 Device and Documentation Support
12.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUP1T34
SN74AUP1T34
www.ti.com
SCES841F – JUNE 2012 – REVISED APRIL 2018
13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
SN74AUP1T34DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
U2Q, U2E
SN74AUP1T34DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
U2
SN74AUP1T34DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
U2
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Product Folder Links: SN74AUP1T34
17
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.5
1.2
4.0
8.0
Q3
SN74AUP1T34DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
SN74AUP1T34DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74AUP1T34DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2021
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1T34DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AUP1T34DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74AUP1T34DSFR
SON
DSF
6
5000
184.0
184.0
19.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/B 06/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/B 06/2022
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.15)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.09 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/B 06/2022
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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