SN74AUP1T97
SCES613J – OCTOBER 2004 – REVISED SN74AUP1T97
SEPTEMBER 2020
SCES613J – OCTOBER 2004 – REVISED SEPTEMBER 2020
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SN74AUP1T97 Single-Supply Voltage-level Translator
With Nine Configurable Gate Logic Functions
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Packages
Single-Supply Voltage Translator
1.8 V to 3.3 V (at VCC = 3.3 V)
2.5 V to 3.3 V (at VCC = 3.3 V)
1.8 V to 2.5 V (at VCC = 2.5 V)
3.3 V to 2.5 V (at VCC = 2.5 V)
Nine Configurable Gate Logic Functions
Schmitt-Trigger Inputs Reject Input Noise and
Provide Better Output Signal Integrity
Ioff Supports Partial-Power-Down Mode With Low
Leakage Current (0.5 µA)
Very Low Static and Dynamic Power Consumption
Pb-Free Packages Available: SON (DRY or DSF),
SOT-23 (DBV), SC-70 (DCK), and NanoStar
WCSP
Latch-Up Performance Exceeds 100 mA Per JESD
78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Related Devices: SN74AUP1T98, SN74AUP1T57,
and SN74AUP1T58
The SN74AUP1T97 can be easily configured to
perform a required gate function by connecting A, B,
and C inputs to VCC or ground (see Function
Selection table). Up to nine commonly used logic gate
functions can be performed.
Ioff is a feature that allows for powered-down
conditions (VCC = 0 V) and is important in portable
and mobile applications. When VCC = 0 V, signals in
the range from 0 V to 3.6 V can be applied to the
inputs and outputs of the device. No damage occurs
to the device under these conditions.
The SN74AUP1T97 is designed with optimized
current-drive capability of 4 mA to reduce line
reflections, overshoot, and undershoot caused by
high-drive outputs.
NanoStar package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
SN74AUP1T97DBV
SOT-23 (6)
2.9mm x 1.6mm
SN74AUP1T97DCK
SC70 (6)
2.0mm x 1.25mm
SN74AUP1T97DRY
SON (6)
1.45mm x 1.0mm
SN74AUP1T97DSF
SON (6)
1.0mm x 1.0mm
SN74AUP1T97YFP
DSBGA (6)
1.0mm x 1.4mm
2 Description
SN74AUP1T97YZP
DSBGA (6)
1.75mm x 1.25mm
AUP technology is the industry's lowest-power logic
technology designed for use in battery-operated or
battery backed-up equipment. The SN74AUP1T97 is
designed for logic-level translation applications with
input switching levels that accept 1.8-V LVCMOS
signals, while operating from either a single 3.3-V or
2.5-V VCC supply.
(1)
•
The wide VCC range of 2.3 V to 3.6 V allows the
possibility of battery voltage drop during system
operation and ensures normal operation between this
range.
A
For all available packages, see the orderable addendum at
the end of the data sheet.
3
4
B
C
1
Y
6
Logic Diagram (Positive Logic)
Schmitt-trigger inputs (ΔVT = 210 mV between
positive and negative input transitions) offer improved
noise immunity during switching transitions, which is
especially useful on analog mixed-mode designs.
Schmitt-trigger inputs reject input noise, ensure
integrity of output signals, and allow for slow input
signal transition.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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intellectual
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SCES613J – OCTOBER 2004 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Thermal Information....................................................5
5.6 Electrical Characteristics.............................................5
5.7 Switching Characteristics............................................6
5.8 Switching Characteristics............................................6
5.9 Switching Characteristics............................................6
5.10 Switching Characteristics..........................................7
5.11 Switching Characteristics.......................................... 7
5.12 Switching Characteristics..........................................7
5.13 Operating Characteristics......................................... 7
5.14 Typical Characteristics.............................................. 8
6 Parameter Measurement Information............................ 9
7 Detailed Description......................................................10
7.1 Functional Block Diagram......................................... 10
7.2 Feature Description...................................................10
7.3 Device Functional Modes..........................................11
8 Device and Documentation Support............................13
8.1 Documentation Support............................................ 13
8.2 Receiving Notification of Documentation Updates....13
8.3 Support Resources................................................... 13
8.4 Trademarks............................................................... 13
8.5 Glossary....................................................................13
9 Mechanical, Packaging, and Orderable Information.. 13
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (May 2010) to Revision J (September 2020)
Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section................................................................................................................................................................ 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the
data sheet........................................................................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
2
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4 Pin Configuration and Functions
B
GND
A
1
6
2
5
3
4
C
VCC
Y
Figure 4-1. DBV OR DCK Package 6-Pin SOT-23 or SC70 Top View
B
1
6
C
GND
2
5
VCC
A
3
4
Y
Figure 4-2. DRY OR DSF Package 6-Pin SON Top View
B
GND
A
A1
1 6
A2
B1
2 5
B2
C
VCC
C1
3 4
C2
Y
Figure 4-3. YFP OR YZP Package 6-Pin DSBGA Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage
–0.5
4.6
V
voltage(2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
VI
Input
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2)
UNIT
VO
Output voltage range in the high or low
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature
–65
V
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
UNIT
2000
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
See(1)
VCC
MIN
MAX
2.3
3.6
UNIT
V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
4
Supply voltage
VCC = 2.3 V
–3.1
VCC = 3 V
–4
VCC = 2.3 V
3.1
VCC = 3 V
4
–40
85
mA
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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5.4 Thermal Information
SN74AUP1T97
THERMAL METRIC(1)
DBV
(SOT-23)
DCK
(SC70)
DRY (SON)
DSF (SON)
6 PINS
6 PINS
6 PINS
6 PINS
165
259
340
300
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
°C/W
ψJB
Junction-to-board characterization parameter
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Thermal Information
SN74AUP1T97
THERMAL
METRIC(1)
YFP (DSBGA)
YZP (DSBGA)
6 PINS
6 PINS
123
123
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
°C/W
RθJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
°C/W
ψJB
Junction-to-board characterization parameter
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
UNIT
MAX
MIN
MAX
VT+
Positive-going
input threshold
voltage
2.3 V to 2.7 V
0.6
1.1
0.6
1.1
3 V to 3.6 V
0.75
1.16
0.75
1.19
VT–
Negative-going
input threshold
voltage
2.3 V to 2.7 V
0.35
0.6
0.35
0.6
3 V to 3.6 V
0.5
0.85
0.5
0.85
ΔVT
Hysteresis
(VT+ – VT–)
2.3 V to 2.7 V
0.23
0.6
0.1
0.6
3 V to 3.6 V
0.25
0.56
0.15
0.56
IOH = –20 µA
IOH = –2.3 mA
VOH
IOH = –3.1 mA
IOH = –2.7 mA
IOH = –4 mA
VOL
2.3 V to 3.6 V
2.3 V
3V
VCC – 0.1
VCC – 0.1
2.05
1.97
1.9
1.85
2.72
2.67
2.6
V
V
V
V
2.55
IOL = 20 µA
2.3 V to 3.6 V
0.1
0.1
IOL = 2.3 mA
2.3 V
0.31
0.33
V
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5.6 Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
All inputs
MAX
MIN
UNIT
MAX
IOL = 3.1 mA
0.44
0.45
0.31
0.33
3V
VI = 3.6 V or GND
Ioff
VI or VO = 0 V to 3.6 V
ΔIoff
VI or VO = 3.6 V
ICC
ΔICC
TYP
IOL = 2.7 mA
IOL = 4 mA
II
TA = –40°C
to 85°C
TA = 25°C
VCC
0.44
0.45
0 V to 3.6 V
0.1
0.5
µA
0V
0.1
0.5
µA
0 V to 0.2 V
0.2
0.5
µA
VI = 3.6 V or GND, IO = 0
2.3 V to 3.6 V
0.5
0.9
µA
One input at 0.3 V or 1.1 V,
Other inputs at 0 or VCC, IO = 0
2.3 V to 2.7 V
4
One input at 0.45 V or 1.2 V,
Other inputs at 0 or VCC, IO = 0
3 V to 3.6 V
12
µA
Ci
VI = VCC or GND
3.3 V
1.5
pF
Co
VO = VCC or GND
3.3 V
3
pF
5.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 1.8 V ± 0.15 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
UNIT
MIN
TYP
MAX
MIN
MAX
5 pF
1.8
2.3
2.9
0.5
6.8
10 pF
2.3
2.8
3.4
1
7.9
15 pF
2.6
3.1
3.8
1
8.7
30 pF
3.8
4.4
5.1
1.5
10.8
ns
5.8 Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 2.5 V ± 0.2 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
UNIT
MAX
5 pF
1.8
2.3
3.1
0.5
6
10 pF
2.2
2.8
3.5
1
7.1
15 pF
2.6
3.2
5.2
1
7.9
30 pF
3.7
4.4
5.2
1.5
10
ns
5.9 Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 3.3 V ± 0.3 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
tpd
6
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
5 pF
2
2.7
3.5
0.5
5.5
10 pF
2.4
3.1
3.9
1
6.5
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UNIT
ns
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5.9 Switching Characteristics (continued)
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 3.3 V ± 0.3 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = –40°C
to 85°C
TA = 25°C
CL
MIN
TYP
MAX
15 pF
2.8
3.5
30 pF
4
4.7
UNIT
MIN
MAX
4.3
1
7.4
5.5
1.5
9.5
5.10 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 1.8 V ± 0.15 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
UNIT
MIN
TYP
MAX
MIN
MAX
1.6
2
2.5
0.5
8
10 pF
2
2.4
2.9
1
8.5
15 pF
2.3
2.8
3.3
1
9.1
30 pF
3.4
3.9
4.4
1.5
9.8
5 pF
tpd
TA = –40°C
to 85°C
TA = 25°C
CL
ns
5.11 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 2.5 V ± 0.2 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
1.6
1.9
2.4
0.5
5.3
10 pF
2
2.3
2.7
1
6.1
15 pF
2.3
2.7
3.1
1
6.8
30 pF
3.4
3.8
4.2
1.5
8.5
5 pF
tpd
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
CL
UNIT
ns
5.12 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 3.3 V ± 0.3 V (unless
otherwise noted) (see Figure 6-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
1.6
2.1
2.7
0.5
4.7
10 pF
2
2.4
3
1
5.7
15 pF
2.3
2.7
3.3
1
6.2
30 pF
3.4
3.8
4.4
1.5
7.8
5 pF
tpd
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
CL
UNIT
ns
5.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
4
5
UNIT
pF
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5.14 Typical Characteristics
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
3
80%
80%
2.5
60%
3.3-V
3.3-V
LVC
Logic†
40%
Voltage − V
100%
60%
40%
Logic†
20%
20%
AUP
0%
†
0%
AUP
Single, dual, and triple gates
Figure 5-1. AUP – The Lowest-Power Family
8
Switching Characteristics
at 25 MHz†
3.5
2
1.5
1
Input
Output
0.5
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 5-2. Excellent Signal Integrity
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6 Parameter Measurement Information
From Output
Under Test
CL
(see Note A)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VI/2
VCC/2
5, 10, 15, 30 pF
VI/2
VCC/2
1 MΩ
CL
VMI
VMO
LOAD CIRCUIT
VI
VMI
Input
VMI
0V
tPHL
tPLH
VOH
VMO
Output
VMo
VOL
tPHL
tPLH
VOH
Output
VMo
VMo
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
Figure 6-1. Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Functional Block Diagram
3
A
4
1
B
Y
6
C
Figure 7-1. Logic Diagram (Positive Logic)
7.2 Feature Description
3.3 V
3.3 V
VIH = 1.19 V
VIL = 0.5 V
VIH = 1.19 V
VIL = 0.5 V
1.8-V
System
3.3-V
System
2.5-V
System
3.3-V
System
SN74AUP1T97
SN74AUP1T97
2.5 V
2.5 V
VIH = 1.10 V
VIL = 0.35 V
VIH = 1.10 V
VIL = 0.35 V
1.8-V
System
2.5-V
System
3.3-V
System
SN74AUP1T97
2.5-V
System
SN74AUP1T97
Figure 7-2. Possible Voltage-Translation Combinations
3.3 V
1.8-V
System
3.3-V
System
SN74AUP1T97
VOH min
VT+ max = VIH min = 1.19 V
VT− min = VIL max = 0.5 V
VOL max
Input Switching Waveform
Output Switching Waveform
Figure 7-3. Switching Thresholds for 1.8-V to 3.3-V Translation
10
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7.3 Device Functional Modes
Table 7-1 lists the functional modes of the SN74AUP1T97.
Table 7-1. Function Table
INPUTS
C
B
A
OUTPUT
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
7.3.1 Logic Configurations
Table 7-2. Function Selection Table
LOGIC FUNCTION
FIGURE NO.
2-to-1 data selector
7-4
2-input AND gate
7-5
2-input OR gate with one inverted input
7-6
2-input NAND gate with one inverted input
7-6
2-input AND gate with one inverted input
7-7
2-input NOR gate with one inverted input
7-7
2-input OR gate
7-8
Inverter
7-9
Noninverted buffer
7-10
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 7-4. 157: 2-to-1 Data Selector/MUX
When C is L, Y = B
When C is H, Y = A
VCC
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 7-5. 08: 2-Input AND Gate
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VCC
C
Y
A
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 7-6. 14+32/14+00: 2-Input OR/NAND Gate With One Inverted Input
VCC
C
Y
B
B
C
Y
B
1
6
2
5
3
4
C
Y
GND
Figure 7-7. 14+08/14+02: 2-Input AND/NOR Gate With One Inverted Input
VCC
C
Y
B
B
1
6
2
5
3
4
C
Y
GND
Figure 7-8. 32: 2-Input OR Gate
VCC
C
Y
1
6
2
5
3
4
C
Y
GND
Figure 7-9. 04/14: Inverter
VCC
B
B
Y
1
6
2
5
3
4
Y
GND
Figure 7-10. 17/34: Noninverted Buffer
12
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Product Folder Links: SN74AUP1T97
SN74AUP1T97
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SCES613J – OCTOBER 2004 – REVISED SEPTEMBER 2020
8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
NanoStar™ and TI E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AUP1T97DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT4R
SN74AUP1T97DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HT4F, HT4R)
SN74AUP1T97DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(THF, THR)
SN74AUP1T97DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(THF, THR)
SN74AUP1T97DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
TH
SN74AUP1T97DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
TH
SN74AUP1T97YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(TH2, THN)
SN74AUP1T97YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(TH2, THN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of