SN74AVC16827DGVR

SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 • FEATURES • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages • • • • DESCRIPTION A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal - Output Voltage - V 2.8 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL - Output Voltage - V 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 2.5 V VCC = 1.8 V -160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA -32 -16 0 Figure 1. Output Voltage vs Output Current This 20-bit noninverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16827 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC, DOC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2005, Texas Instruments Incorporated SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 TERMINAL ASSIGNMENTS DGG OR DGV PACKAGE (TOP VIEW) 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 1Y7 GND 1Y8 1Y9 1Y10 2Y1 2Y2 2Y3 GND 2Y4 2Y5 2Y6 VCC 2Y7 2Y8 GND 2Y9 2Y10 2OE1 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2A10 2OE2 FUNCTION TABLE (EACH 10-BIT BUFFER/DRIVER) INPUTS 2 A OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 LOGIC SYMBOL(1) 1OE1 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1 & EN1 56 28 & EN2 29 55 1 2 1 54 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 1 2 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 1Y10 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 2Y10 (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (POSITIVE LOGIC) 1OE1 1OE2 1A1 28 2OE1 29 2OE2 1 56 55 2 1Y1 To Nine Other Channels 2A1 42 15 2Y1 To Nine Other Channels 3 SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V –0.5 4.6 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 64 DGV package 48 –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions VCC Supply voltage VCC = 1.2 V VIH High-level input voltage MIN MAX 1.2 3.6 0.65 × VCC VCC = 1.65 V to 1.95 V 0.65 × VCC VCC = 3 V to 3.6 V Low-level input voltage VI 2 Output voltage IOHS Static high-level output current (1) GND VCC = 1.4 V to 1.6 V 0.35 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 Input voltage VO 0 3.6 Active state 0 VCC 3-state 0 3.6 VCC = 1.4 V to 1.6 V –2 VCC = 1.65 V to 1.95 V –4 VCC = 2.3 V to 2.7 V –8 VCC = 3 V to 3.6 V IOLS Static low-level output current (1) ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 4 V V V mA –12 VCC = 1.4 V to 1.6 V 2 VCC = 1.65 V to 1.95 V 4 VCC = 2.3 V to 2.7 V 8 VCC = 3 V to 3.6 V (1) V 1.7 VCC = 1.2 V VIL V VCC VCC = 1.4 V to 1.6 V VCC = 2.3 V to 2.7 V UNIT mA 12 VCC = 1.4 V to 3.6 V –40 5 ns/V 85 °C Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 3.3-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VCC IOHS = –100 µA, VIH = VCC IOHS = –2 mA, VIH = 0.91 V 1.4 V IOHS = –4 mA, VIH = 1.07 V 1.65 V 1.2 IOHS = –8 mA, VIH = 1.7 V 2.3 V 1.75 IOHS = –12 mA, VIH = 2 V 3V 2.3 1.4 V to 3.6 V IOLS = 100 µA VOL MIN TYP (1) MAX UNIT VCC – 0.2 1.05 V 1.4 V to 3.6 V 0.2 IOLS = 2 mA, VIL = 0.49 V 1.4 V 0.4 IOLS = 4 mA, VIL = 0.57 V 1.65 V 0.45 IOLS = 8 mA, VIL = 0.7 V 2.3 V 0.55 IOLS = 12 mA, VIL = 0.8 V 3V 0.7 V II VI = VCC or GND 3.6 V ±2.5 µA Ioff VI or VO = 3.6 V 0 ±10 µA IOZ VO = VCC or GND, VIH = VCC 3.6 V ±12.5 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA Control inputs 2.5 V VI = VCC or GND Ci Co (1) Data inputs VI = VCC or GND Outputs VO = VCC or GND 4 3.3 V 4 2.5 V 2.5 3.3 V 2.5 2.5 V 6.5 3.3 V 6.5 pF pF Typical values are measured at TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5) FROM (INPUT) TO (OUTPUT) tpd A ten OE tdis OE PARAMETER VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX Y 3 0.4 3.2 0.9 2.9 0.8 1.9 0.5 1.7 ns Y 8.7 2.3 9.1 2.1 8 1.4 5.6 1.2 5.1 ns Y 7.5 2.7 8.3 2.5 7.3 0.9 4.9 1 4.7 ns Switching Characteristics (1) TA = 0°C to 85°C, CL = 0 pF PARAMETER tpd (1) FROM (INPUT) TO (OUTPUT) A Y VCC = 3.3 V ± 0.15 V MIN MAX 0.09 0.67 UNIT ns Texas Instruments SPICE simulation data Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 31 35 40 6 6 6 UNIT pF 5 SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 15 pF (see Note A) 2 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VOH VCC/2 VOH − 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 7 SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 8 SN74AVC16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES176I – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw LOAD CIRCUIT VCC VCC Timing Input VCC/2 Input VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) VCC VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VOL + 0.3 V VOL tPZH tPHL VCC/2 Output Waveform 2 S1 at GND (see Note B) tPHZ VCC/2 VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AVC16827DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16827 SN74AVC16827DGVR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CVA827 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of