SN74BCT29854DWRE4

      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 • • • • • • • • DW OR NT PACKAGE (TOP VIEW) BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to AMD Am29854 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Latch for Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE description The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic. The SN74BCT29854 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT AND I/O Bi† ∑ of L’s A B PARITY ERR‡ FUNCTION OEB OEA CLR LE Ai ∑ of H’s L H X X Odd Even NA NA A H L NA H L X L NA Odd Even B NA NA H L H L H H NA X X NA NA N−1 X X L H X X X NA NA H H H H L X X H H L L X X L Odd H Even X Z Z Z NC H L H Isolation§ L L X X Odd Even NA NA A L H NA A data to B bus and generate inverted parity A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error-flag register NA = not applicable, NC = no change, X = don’t care † Summation of low-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume the ERR output was previously high. § In this mode, the ERR output, when enabled, shows noninverted parity of the A bus. Copyright  1993, Texas Instruments Incorporated    ! " #$%! "  &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%"  %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"* • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2−1 
      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 logic diagram (positive logic) A1 −A8 8x 8 8 B1 −B8 EN 8x 8 EN OEB 8 OEA PARITY 8 MUX 1 1 2k 9 P 1 1 G1 ERR LE CLR 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 error-flag waveforms OEB H L OEA H L Even Bi + PARITY Odd LE H L CLR H L ERR H L Pass Sample Store Clear ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRESTATE OUTPUT FUNCTION LE CLR POINT P ERRn−1† ERR L L L H X L H Pass L H L X H X L H L L H Sample H L X X H Clear X L H L H Store H H † ERRn−1 represents the state of the ERR output before any changes at CLR, LE, or point P. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−3 
      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 recommended operating conditions VCC VIH Supply voltage VIL VOH Low-level input voltage IOH IOL High-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX 4.5 5 5.5 2 V V 0.8 High-level output voltage UNIT ERR Low-level output current 0 V 2.4 V −24 mA 48 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VOH All inputs /outputs except ERR VCC = 4.5 V IOH VOL ERR VCC = 4.5 V, VCC = 4.5 V, II IIH‡ IIL‡ MIN II = −18 mA IOH = − 15 mA IOH = − 24 mA VOH = 2.4 V TYP† V V 2 20 0.35 µA 0.5 V 0.1 mA VI = 2.7 V 20 µA VCC = 5.5 V, VI = 0.4 V −0.75 VCC = 5.5 V, VCC = 5.5 V, VO = 0 Outputs open Data IOS§ ICCL UNIT −1.2 2.4 IOL = 48 mA VI = 5.5 V VCC = 5.5 V, VCC = 5.5 V, Control MAX −0.2 −75 ICCZ VCC = 5.5 V, Outputs open † All typical values are at VCC = 5 V, TA = 25°C. ‡ These parameters include off-state output current for I/O ports only. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. mA −250 mA 55 80 mA 30 45 mA timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN LE low 10 CLR low 10 MAX UNIT tw Pulse duration tsu Setup time before LE↓ Bi and PARITY 18 ns th Hold time after LE↓ Bi and PARITY 8 ns 2−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns 
      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPZH tPZL OEA or OEB A or B tPHZ tPLZ OEA or OEB A or B PARAMETER tPLH tPHL CLR ERR LE tPLH tPHL OEA PARITY tPLH tPHL Bi / PARITY ERR VCC = 5 V, TA = 25°C MIN MAX 7 1 8 5 7 1 8 1.5 10 13 1.5 15 1.5 10 13 1.5 15 2 12 15 2 17 2 13 16 2 19 2 8 11 2 15 2 10 14 2 17 1.5 11 13 1.5 15 1.5 5 7 1.5 9 1.5 10 13 1.5 15 1.5 10 13 1.5 16 1.5 15 18 1.5 20 1.5 10 13 1.5 15 MIN TYP MAX 1 5 1 UNIT ns ns ns ns ns ns ns NOTE 1: Load circuits and voltage waveforms are shown in Section 1. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−5 
      

   SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 2−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74BCT29854DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 BCT29854 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of