SN74CB3Q32245GKER

    

       SCES622 – JANUARY 2005 D Member of the Texas Instruments D D D D D D D D Data and Control Inputs Provide Widebus+ Family High-Bandwidth Data Path (Up to 500 MHz†) 5-V-Tolerant I/Os with Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 5 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 4 pF Typical) Fast Switching Frequency (fOE = 20 MHz Max) D D D D D D D D † For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008. Undershoot Clamp Diodes Low Power Consumption (ICC = 2 mA Typical) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating description/ordering information The SN74CB3Q32245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q32245 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q32245 is organized as four 8-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 8-bit bus switches, two 16-bit bus switches, or as one 32-bit bus switch. When OE is low, the associated 8-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 8-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE‡ TA LFBGA − GKE Tape and reel SN74CB3Q32245GKER LFBGA − ZKE (Pb-free) Tape and reel SN74CB3Q32245ZKER TOP-SIDE MARKING BZ245 ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright  2005, Texas Instruments Incorporated     !" # $%&" !#  '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&#  &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/  !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
    

       SCES622 – JANUARY 2005 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 8-bit bus switch) GKE PACKAGE (TOP VIEW) 1 3 4 5 INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect terminal assignments 6 1 2 3 4 5 6 A A 1B2 1B1 NC 1OE 1A1 1A2 B B 1B4 1B3 GND GND 1A3 1A4 C C 1B6 1B5 1A6 1B8 1B7 VCC GND 1A5 D VCC GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 F 2B4 2B3 2A4 2B6 2B5 VCC GND 2A3 G VCC GND 2A5 2A6 H 2B7 2B8 NC 2OE 2A8 2A7 D E F G H J 3B2 3B1 NC 3OE 3A1 3A2 J K 3B4 3B3 GND GND 3A3 3A4 K L 3B6 3B5 3A6 M 3B8 3B7 VCC GND 3A5 L VCC GND 3A7 3A8 M N 4B2 4B1 GND GND 4A1 4A2 N P 4B4 4B3 4B6 4B5 VCC GND 4A4 R VCC GND 4A3 P 4A5 4A6 R T 4B7 4B8 NC 4OE 4A8 4A7 T 2 2 INPUT OE NC − No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    

       SCES622 – JANUARY 2005 logic diagram (positive logic) A2 A5 1A1 SW 2A1 1B8 2A8 D1 D6 1A8 SW E2 E5 1B1 H2 H5 A4 2B1 SW 2B8 SW H4 1OE 2OE J5 3A1 J2 SW 4A1 3B8 4A8 M1 M6 3A8 N5 3B1 SW N2 T2 T5 J4 4B1 SW SW 4B8 T4 3OE 4OE simplified schematic, each FET switch (SW) A B VCC Charge Pump EN† † EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    

       SCES622 – JANUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±64 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground, unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O TA Data input/output voltage MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 1.7 5.5 2 5.5 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V −40 85 °C Operating free-air temperature UNIT V V V NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    

       SCES622 – JANUARY 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK IIN TEST CONDITIONS MIN VCC = 3.6 V, VCC = 3.6 V, II = −18 mA VIN = 0 to 5.5 V IOZ‡ VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VI = 0 ICC VCC = 3.6 V, VO = 0 to 5.5 V, II/O = 0, Switch ON or OFF, Control inputs ∆ICC§ Control inputs ICCD¶ Per control input VCC = 3.6 V, One input at 3 V, VCC = 3.6 V, A and B ports open, Control input switching at 50% duty cycle Cin Control inputs VCC = 3.3 V, VIN = VCC or GND TYP† 2 Other inputs at VCC or GND MAX UNIT −1.8 V ±1 µA ±1 µA 1 µA 4 mA 30 VIN = 5.5 V, 3.3 V, or 0 Switch OFF, VI/O = 5.5 V, 3.3 V, or 0 VIN = VCC or GND, 0.15 0.25 3.5 5 pF 4 6 pF 10 13 pF Cio(OFF) VCC = 3.3 V, Cio(ON) VCC = 3.3 V, Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0, VI = 1.7 V, IO = 30 mA IO = −15 mA 6 8 5 10 VCC = 3 V VI = 0, VI = 2.4 V, IO = 30 mA IO = −15 mA 6 8 5 9 ron# µA mA/ MHz Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER fOE|| tpdk ten FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX OE A or B 10 20 MHz A or B B or A 0.18 0.3 ns OE A or B 7 ns 1.5 8 1.5 tdis A or B 1 8 1 7 ns OE || Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) k The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
    

       SCES622 – JANUARY 2005 ron − ON−State Resistance − Ω 16 VCC = 3.3 V TA = 25°C IO = −15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI − V Figure 1. Typical ron vs VI 12 VCC = 3.3 V TA = 25°C A and B ports Open 10 ICC − mA 8 6 4 One OE Switching 2 0 0 2 4 6 8 10 12 14 OE Switching Frequency − MHz Figure 2. Typical ICC vs OE Switching Frequency 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 18 20 
    

       SCES622 – JANUARY 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT Input Generator VI S1 RL VO 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V Output Control (VIN) V∆ VCC VCC/2 VCC VCC/2 0V tPLH VOH Output VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 tPZH tPHL VCC/2 VOL VCC/2 0V tPZL VCC/2 Open GND 50 Ω Output Control (VIN) 2 × VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CB3Q32245ZKER OBSOLETE LFBGA ZKE 96 TBD Call TI Call TI BZ245 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of