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SN74CB3Q3253
SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
SN74CB3Q3253 Dual 1-of-4 FET Multiplexer – Demultiplexer
2.5-V – 3.3-V Low-Voltage High-Bandwidth Bus Switch
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
3 Description
(1)
High-Bandwidth Data Path (Up to 500 MHz)
5-V Tolerant I/Os With Device Powered Up or
Powered Down
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 4 Ω Typical)
Rail-to-Rail Switching on Data I/O Ports
– 0- to 5-V Switching With 3.3-V VCC
– 0- to 3.3-V Switching With 2.5-V VCC
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes Loading
and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
Fast Switching Frequency (fOE = 20 MHz Max)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 0.6 mA Typical)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signal Levels (0.8-V,
1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can be Driven by TTL or 5-V and
3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog Applications:
USB Interface, Differential Signal Interface Bus
Isolation, Low-Distortion Signal Gating
The SN74CB3Q3253 device is a high-bandwidth FET
bus switch using a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat
ON-state resistance (ron). The low and flat ON-state
resistance allows for minimal propagation delay and
supports rail-to-rail switching on the data input and
output (I/O) ports.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74CB3Q3253DBQ SSOP (16)
4.90 mm × 3.90 mm
SN74CB3Q3253DGV TVSOP (16)
3.60 mm × 4.40 mm
SN74CB3Q3253RGY VQFN (16)
4.00 mm × 3.50 mm
SN74CB3Q3253PW
5.00 mm × 4.40 mm
TSSOP (16)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
7
1A
6
SW
5
SW
1B1
1B2
4
SW
1B3
3
1B4
SW
10
9
2A
2B1
SW
11
SW
2B2
12
2B3
SW
13
SW
2B4
14
S0
2
S1
1
1OE
2OE
15
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report CBT-C, CB3T, and CB3Q Signal-Switch Families,
(SCDA008).
2 Applications
•
•
Video Broadcasting: IP-Based Multi-Format
Transcoder
Video Communications System
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3Q3253
SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
Changes from Revision B (June 2015) to Revision C
Page
•
Changed the pinout image appearance ................................................................................................................................ 3
•
Updated the Thermal Information table ................................................................................................................................. 5
Changes from Revision A (November 2003) to Revision B
Page
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications, Device Information table, Pin Configuration and Functions section, Storage Conditions table,
ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
2
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SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
5 Pin Configuration and Functions
DBQ, DGV, or PW Package
16-Pin SSOP, TVSOP, or TSSOP
Top View
VCC
S1
2
15
2OE
1B4
3
14
S0
1B3
4
13
2B4
1B2
5
12
2B3
1B1
6
11
2B2
S1
2
1B4
3
1B3
4
1B2
VCC
16
16
1
1OE
1OE
1
RGY Package
16-Pin VQFN
Top View
15
2OE
14
S0
13
2B4
5
12
2B3
1B1
6
11
2B2
1A
7
10
2B1
Thermal
2B1
GND
8
9
2A
9
10
2A
7
GND
1A
8
Pad
Not to scale
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1OE
1
I
Output Enable 1 Active-Low
S1
2
I
Select Pin 1
1B4
3
I/O
Channel 1 I/O 4
1B3
4
I/O
Channel 1 I/O 3
1B2
5
I/O
Channel 1 I/O 2
1B1
6
I/O
Channel 1 I/O 1
1A
7
I/O
Channel 1 common
GND
8
—
Ground
2A
9
I/O
Channel 2 common
2B1
10
I/O
Channel 2 I/O 1
2B2
11
I/O
Channel 2 I/O 2
2B3
12
I/O
Channel 2 I/O 3
2B4
13
I/O
Channel 2 I/O 4
S0
14
I
Select Pin 0
2OE
15
I
Output Enable 2 Active-Low
VCC
16
—
Power
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SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4.6
V
VIN
Control input voltage
(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±64
mA
Continuous current through VCC or GND
±100
mA
150
°C
VCC
Supply voltage
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
+2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
+1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
4
MIN
MAX
2.3
3.6
UNIT
VCC = 2.3 V to 2.7 V
1.7
5.5
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).
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6.4 Thermal Information
SN74CB3Q3253
THERMAL METRIC
DBQ
(SSOP)
DGV
(TVSOP)
PW
(TSSOP)
RGY
(VQFN)
16 PINS
16 PINS
16 PINS
16 PINS
(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
114.3
126
112.7
45.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
65.4
51.3
47.5
59.6
°C/W
RθJB
Junction-to-board thermal resistance
56.8
57.8
57.85
23.3
°C/W
ψJT
Junction-to-top characterization parameter
18.3
5.9
6
2.2
°C/W
ψJB
Junction-to-board characterization parameter
56.4
57.3
57.3
23.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
11.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIK
MIN TYP (2)
TEST CONDITIONS
MAX
UNIT
VCC = 3.6 V,
II = –18 mA
VCC = 3.6 V,
VIN = 0 to 5.5 V
IOZ (3)
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC or
GND
VCC = 3.6 V,
A and B ports open,
OE input
0.15
0.16
S input
0.04
0.05
mA/
MHz
2.5
3.5
pF
IIN
Control inputs
ICC
ΔICC (4)
Control inputs
ICCD (5)
Per control input
Cin
Control inputs
Control input switching at 50% duty cycle
ron (6)
(6)
µA
±1
µA
1
µA
2
mA
30
µA
VIN = 5.5 V, 3.3 V, or 0
A port
VCC = 3.3 V,
Switch OFF,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
8
11
pF
B port
VCC = 3.3 V,
Switch OFF,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
3.5
4.5
pF
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
13
17
pF
VI = 0,
IO = 30 mA
4
10
VI = 1.7 V,
IO = –15 mA
4.5
11
VI = 0,
IO = 30 mA
3.5
8
VI = 2.4 V,
IO = –15 mA
4
10
VCC = 2.3 V,
TYP at VCC = 2.5 V
VCC = 3 V
(1)
(2)
(3)
(4)
(5)
V
±1
VCC = 3.3 V,
Cio(OFF)
Cio(ON)
0.6
–1.8
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
f OE or fS (1)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX
OE or S
A or B
10
20
tpd (2)
A or B
B or A
0.12
0.18
ns
tpd(s)
S
A
1.5
6.7
1.5
5.9
ns
S
B
1.5
6.7
1.5
5.9
OE
A or B
1.5
6.7
1.5
5.9
ten
tdis
(1)
(2)
S
B
1
6.1
1
6.1
OE
A or B
1
6.1
1
6.1
MHz
ns
ns
Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0).
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
16
12
14 VCC = 3.3 V
TA = 25°C
12 IO = -15 mA
10
8
6
6
4
One S Switching
4
2
2
One OE Switching
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VI - V
Figure 1. Typical ron vs VI, VCC = 3.3 V and IO = –15 mA
6
VCC = 3.3 V
TA = 25°C
A and B ports Open
8
10
ICC - mA
Ron ± ON-State Resistance - Ÿ
6.7 Typical Characteristics
0
2
4
6
8 10 12 14 16 18
OE or S Switching Frequency - MHz
20
Figure 2. Typical ICC vs OE or S Switching Frequency,
VCC = 3.3 V
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
GND
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
VCC
VCC
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + VD
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
VOH
VCC/2
VOH − VD
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as t dis.
F. t PZL and tPZH are the same as t en.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CB3Q3253 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state
resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O)
ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on
the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3253 device provides
an optimized interface solution ideally suited for broadband communications, networking, and data-intensive
computing systems.
The SN74CB3Q3253 device is organized as two 1-of-4 multiplexers/demultiplexers with separate output-enable
(1OE, 2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE
is low, the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing
bidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled, and
a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
B
A
VCC
Charge
Pump
EN(1)
(1) EN is the internal enable signal applied to the switch.
Figure 4. Simplified Schematic, Each FET Switch (SW)
8
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8.2 Functional Block Diagram
7
6
1A
SW
5
SW
1B1
1B2
4
SW
1B3
3
1B4
SW
10
9
2A
2B1
SW
11
SW
2B2
12
2B3
SW
13
SW
2B4
14
S0
2
S1
1
1OE
2OE
15
8.3 Feature Description
The SN74CB3Q3253 device has a high-bandwidth data path (up to 500 MHz) and has 5-V tolerant I/Os with the
device powered up or powered down. It also has low and flat ON-state resistance (ron) characteristics over
operating range (ron = 4 Ω Typical)
This device also has rail-to-rail switching on data I/O ports for 0- to 5-V switching with 3.3-V VCCand 0- to 3.3-V
switching with 2.5-V VCCas well as bidirectional data flow with near-zero propagation delay and low input and
output capacitance that minimizes loading and signal distortion (Cio(OFF) = 3.5 pF Typical)
The SN74CB3Q3253 also provides a fast switching frequency (fOE = 20 MHz Maximum) with data and control
inputs that provide undershoot clamp diodes as well as low power consumption (ICC = 0.6 mA Typical)
The VCC operating range is from 2.3 V to 3.6 V and the data I/Os support 0- to 5-V signal levels of (0.8-V, 1.2-V,
1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
The control inputs can be driven by TTL or 5-V and 3.3-V CMOS outputs as well as Ioff Supports Partial-PowerDown Mode Operation
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74CB3Q3253.
Table 1. Function Table
(Each Multiplexer/Demultiplexer)
INPUTS
OE
S1
L
L
L
L
H
INPUT/OUTPUT
FUNCTION
S0
A
L
L
B1
A port = B1 port
L
H
B2
A port = B2 port
H
L
B3
A port = B3 port
H
H
B4
A port = B4 port
X
X
Z
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74CB3Q3253 device can be used to multiplex and demultiplex up to 4 channels simultaneously in a 2:1
configuration.
9.2 Typical Application
The application shown here is a 4-bit bus being multiplexed between two devices. the OE and S pins are used to
control the chip from the bus controller. This is a very generic example, and could apply to many situations. If an
application requires less than 4 bits, be sure to tie the A side to either high or low on unused channels.
VCC
SN74CB3Q3253
S0
S1
1A
14
Switch
Select
2
7
RON
S1 S0
L L
L H
6
5
H L
H H
Bus
Controller
16
4
3
2
S1 S0
L L
4A
1OE
2OE
GND
9
RON
L H
10
11
H L
H H
12
1
13
VCC
1B1
0.1 PF
2
1B2
Device 1
1B3
2
1B4
Device 2
2B1
2
2B2
Device 3
2B3
2
2B4
Device 4
15
8
Figure 5. Typical Application of the SN74CB3Q3253
9.2.1 Design Requirements
The 0.1-µF capacitor should be place as close as possible to the device.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Inputs and outputs are overvoltage tolerant slowing them to go as high as 4.6 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed ±128 mA per channel.
3. Frequency Selection Criterion:
– Maximum frequency tested is 500 MHz.
– Added trace resistance and capacitance can reduce maximum frequency capability; use layout practices
as directed in Layout.
10
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SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
Typical Application (continued)
9.2.3 Application Curve
Voltage (V)
3
2
1
VIN
VOUT
0
0
100 200 300 400 500 600 700 800 900 1000
Time (ps)
C001
Figure 6. Propagation Delay (tpd) Simulation Result at VCC = 2.5 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
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11
SN74CB3Q3253
SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
www.ti.com
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 7. Trace Example
12
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SN74CB3Q3253
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SCDS145C – OCTOBER 2003 – REVISED JUNE 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74CB3Q3253
13
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CB3Q3253DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BU253
Samples
SN74CB3Q3253DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU253
Samples
SN74CB3Q3253PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU253
Samples
SN74CB3Q3253PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU253
Samples
SN74CB3Q3253PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU253
Samples
SN74CB3Q3253PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU253
Samples
SN74CB3Q3253RGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BU253
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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