SN74CB3Q3306DR

  
       

 SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002 D Low and Flat On-State Resistance (ron) D D D D D D D D High-Bandwidth Data Path (Up To 533 MHz) D Low Power Consumption Characteristics Over Operating Range (ron = 4 Ω Typical) 0- to 5-V Rail-to-Rail Switching on Data I/O Ports VCC Operating Range From 2.3 V to 3.6 V TTL- and LVTTL-Compatible Data I/O Ports LVTTL-Compatible Control Inputs Bidirectional Data Flow With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio = 3.5 pF Typical) Fast Switching Speeds (fOE = 20 MHz Max) (ICC = 250 µA Typical) D Ioff on A and B Port for Partial-Power-Down D D D D Operation Data and Control Inputs Provide Undershoot Clamp Diodes Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Hot Plug, Hot Docking, Memory Interleaving, Bus Isolation, and Low-Distortion Signal Gating D OR PW PACKAGE (TOP VIEW) 1OE 1A 1B GND 1 8 2 7 3 6 4 5 VCC 2OE 2B 2A description/ordering information Texas Instruments bus switches provide high-performance, low-power replacements for standard bus-interface devices when signal buffering (current drive) is not required. The CB3Q family of high-bandwidth bus switches offers low and flat on-state resistance (ron), 0- to 5-V rail-to-rail switching on the data input/output (I/O) ports, and low data I/O capacitance (Cio) to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the CB3Q family provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q3306 is a dual FET bus switch featuring independent line switches. Each switch is enabled when the associated output-enable (OE) input is low, allowing bidirectional data flow between ports A and B. Each switch is disabled when the associated OE input is high, producing a high-impedance state between ports A and B. The very low ron of the switch allows connections to be made with minimal propagation delay. ORDERING INFORMATION –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – D Tube SN74CB3Q3306D Tape and reel SN74CB3Q3306DR TOP-SIDE MARKING BU306 TSSOP – PW Tape and reel SN74CB3Q3306PWR BU306 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated     !"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(, %$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"0'%0 3'%%'"(4 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
  
       

 SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each bus switch) INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 1A 2 3 1B 1 1OE 5 6 2B 2A 7 2OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VIH High le el control inp High-level inputt voltage oltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Lo le el control inp Low-level inputt voltage oltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 UNIT V 1.7 V 2 0.7 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
       

 SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK IIN Control inputs IOZ‡ Ioff ICC ∆ICC§ Control inputs TEST CONDITIONS MIN MAX UNIT VCC = 3.6 V, VCC = 3.6 V, II = –18 mA VIN = 5.5 V or GND –1.8 V ±1 µA VCC = 3.6 V, VCC = 0, VI/O = VCC or GND VI/O = 0 to 5.5 V ±1 µA ±1 µA VCC = 3.6 V, VCC = 3.6 V, II/O = 0, One input at 3 V, 700 µA 25 µA 0.03 0.1 mA/ MHz VIN = VCC or GND Other inputs at VCC or GND 250 VCC = 3.6 V, A and B pins open, Per OE control input switching at 50% duty cycle ICCD¶ Cin Control inputs Cio(OFF) VIN = 5.5 V, 3.3 V, or 0, VI/O = 5.5 V, 3.3 V, or 0, VCC = 3.3 V VCC = 3.3 V, Cio(ON) VI/O = 5.5 V, 3.3 V, or 0, VCC = 3.3 V, VI = 0, VCC = 2.3 V, TYP at VCC = 2.5 V ron# TYP† VI = 1.7 V, VI = 0, VCC = 3 V 2.5 3.5 pF Switch off, OE = VCC 3.5 5 pF Switch on, OE = GND 8 10.5 pF IO = 30 mA IO = –15 mA 4 8 5 9 IO = 30 mA IO = –15 mA 4 6 Ω VI = 2.4 V, 5 8 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single OE control input. The total ICC can be calculated with the following formula: Total ICC = ICC + (ICCD × 1OE frequency) + (ICCD × 2OE frequency). # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER fOE|| tpdk ten FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX OE A or B 10 20 MHz A or B B or A 0.2 0.2 ns OE A or B 5.5 ns 1.5 6.5 1.5 tdis A or B 1 6 1 5 ns OE || Maximum toggle frequency for OE control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) k The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
  
       

 SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002 TYPICAL ron vs VI ron – On-State Resistance – Ω 16 VCC = 3.3 V TA = 25°C IO = –15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI – V Figure 1. Typical ron vs VI, VCC = 3.3 V and IO = –15 mA TYPICAL ICC vs OE SWITCHING FREQUENCY 12 VCC = 3.3 V TA = 25°C ICC – mA 10 8 6 4 All OE Switching One OE Switching 2 0 0 2 4 6 8 10 12 14 16 OE Switching Frequency – MHz Figure 2. Typical ICC vs OE Switching Frequency, VCC = 3.3 V 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 18 20 
  
       

 SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ± 0.2 V 3.3 V ± 0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V t Output PZL Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL VCC Output Control tPLZ VCC VCC/2 VOL + V∆ VOL tPHZ tPZH VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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