SN74CBT3253PW

SN74CBT3253 DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER SCDS018O − MAY 1995 − REVISED JANUARY 2004 D TTL-Compatible Input Levels 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE S0 2B4 2B3 2B2 2B1 2A S1 1B4 1B3 1B2 1B1 1A VCC 16 2 1 16 15 2OE 14 S0 2 3 13 2B4 12 2B3 4 5 11 2B2 10 2B1 6 7 8 9 2A 1 GND 1OE S1 1B4 1B3 1B2 1B1 1A GND 1OE RGY PACKAGE (TOP VIEW) D, DB, DBQ, OR PW PACKAGE (TOP VIEW) description/ordering information The SN74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data. ORDERING INFORMATION QFN − RGY SN74CBT3253RGYR Tube SN74CBT3253D Tape and reel SN74CBT3253DR SSOP − DB Tape and reel SN74CBT3253DBR CU253 SSOP (QSOP) − DBQ Tape and reel SN74CBT3253DBQR CU253 Tube SN74CBT3253PW Tape and reel SN74CBT3253PWR TSSOP − PW † TOP-SIDE MARKING Tape and reel SOIC − D −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA CU253 CBT3253 CU253 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS FUNCTION 1OE 2OE S1 S0 X H X X H X X X Disconnect 1A and 2A L L L L 1A to 1B1 and 2A to 2B1 L L L H 1A to 1B2 and 2A to 2B2 L L H L 1A to 1B3 and 2A to 2B3 L L H H 1A to 1B4 and 2A to 2B4 Disconnect 1A and 2A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBT3253 DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER SCDS018O − MAY 1995 − REVISED JANUARY 2004 logic diagram (positive logic) 1A 6 7 1B1 5 1B2 4 1B3 3 1B4 2A 10 9 2B1 11 2B2 12 2B3 13 2B4 14 S0 S1 2 1 1OE 15 2OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT3253 DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER SCDS018O − MAY 1995 − REVISED JANUARY 2004 recommended operating conditions (see Note 4) MIN MAX 5.5 VCC Supply voltage 4 VIH High-level control input voltage 2 VIL Low-level control input voltage TA Operating free-air temperature −40 UNIT V V 0.8 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, II = −18 mA II VCC = 5 V, VI = 5.5 V or GND ICC MIN VCC = 5.5 V, IO = 0, VI = VCC or GND ΔICC‡ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs VI = 3 V or 0 B port ron§ MAX UNIT −1.2 V ±1 μA 3 μA 2.5 mA 3.5 A port Cio(OFF) TYP† pF 10 VO = 3 V or 0 0, OE = VCC VI = 0 VCC = 4.5 V VI = 2.4 V, pF 4 II = 64 mA 5 II = 30 mA 5 7 7 II = 15 mA 10 15 Ω † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. ‡ switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) VCC = 5 V ± 0.5 V MIN MIN TO (OUTPUT) tpd¶ A or B B or A 0.35 0.25 ns tpd S A or B 6.6 1.6 6.2 ns 7.1 1.3 6.3 7.3 1.4 6.4 7.9 1.1 7.4 7.3 2.3 7 S ten OE A or B S tdis ¶ VCC = 4 V FROM (INPUT) PARAMETER MAX UNIT MAX A or B OE ns ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBT3253 DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER SCDS018O − MAY 1995 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) S1 Open 7V Open 500 Ω 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPZL 3V 1.5 V Input 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74CBT3253D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253 Samples SN74CBT3253DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CU253 Samples SN74CBT3253DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU253 Samples SN74CBT3253DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253 Samples SN74CBT3253DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253 Samples SN74CBT3253PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU253 Samples SN74CBT3253PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU253 Samples SN74CBT3253RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CU253 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of