SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
D 5-Ω Switch Connection Between Two Ports
D TTL-Compatible Input Levels
D Designed to Be Used in Level-Shifting
D OR PW PACKAGE
(TOP VIEW)
1OE
1A
1B
GND
Applications
description/ordering information
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
The SN74CBTD3306 features two independent
line switches. Each switch is disabled when the
associated output-enable (OE) input is high. A
diode to VCC is integrated on the chip to allow for
level shifting from 5-V signals at the device inputs
to 3.3-V signals at the device outputs.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
Tube
SN74CBTD3306D
Tape and reel
SN74CBTD3306DR
Tube
SN74CBTD3306PW
Tape and reel
SN74CBTD3306PWR
SOIC − D
−40°C
40°C to 85°C
TSSOP − PW
†
TOP-SIDE
MARKING
CC306
CC306
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
1A
1OE
2
3
1B
1
5
6
2A
2B
7
2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
MIN
MAX
4.5
5.5
2
−40
UNIT
V
V
0.8
V
85
°C
In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting
effect.
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 4.5 V,
VOH
See Figure 2
II
VCC = 5.5 V,
VI = 5.5 V or GND
ICC
MIN
TYP‡
II = −18 mA
MAX
UNIT
−1.2
V
±1
μA
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
1.5
mA
ΔICC§
Control inputs
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
2.5
mA
Ci
Control inputs
VI = 3 V or 0
Cio(OFF)
ron¶
VO = 3 V or 0,
VCC = 4.5 V
3
OE = VCC
VI = 0
VI = 2.4 V,
pF
4
pF
II = 64 mA
5
7
II = 30 mA
5
7
II = 15 mA
35
50
‡
Ω
All typical values are at VCC = 5 V, TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd†
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
MIN
MAX
UNIT
0.25
ns
2.1
5.4
ns
1
4.7
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
S1
Open
7V
Open
500 Ω
3V
Output
Control
LOAD CIRCUIT
1.5 V
0V
tPZL
3V
1.5 V
Input
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
3.5 V
1.5 V
tPZH
tPHL
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
4
3.75
100 μA
3.75
3.5
6 mA
12 mA
3.5
3.25
24 mA
3
2.75
2.5
2.25
2
1.75
1.5
4.5
VOH − Output Voltage High − V
VOH − Output Voltage High − V
TA = 85°C
TA = 25°C
100 μA
6 mA
12 mA
24 mA
3.25
3
2.75
2.5
2.25
2
1.75
4.75
5
5.25
5.5
5.75
1.5
4.5
4.75
VCC − Supply Voltage − V
5
VCC − Supply Voltage − V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
TA = 0°C
VOH − Output Voltage High − V
3.75
3.5
100 μA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
VCC − Supply Voltage − V
Figure 2. VOH Values
4
5.25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5.5
5.75
5.5
5.75
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74CBTD3306D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306PWG4
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
CC306
SN74CBTD3306PWRG3
PREVIEW
TSSOP
PW
8
2000
TBD
Call TI
Call TI
-40 to 85
SN74CBTD3306PWRG4
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CC306
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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