SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Standard ’16245-Type Pinout
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Ioff Supports Partial-Power-Down Mode
Operation
Active-Clamp Undershoot-Protection
Circuit on the I/Os Clamps Undershoots up
to –2 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
NC
description
The SN74CBTK16245 device provides 16 bits of
high-speed TTL-compatible bus switching in a
standard ’16245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The A and B ports have an active-clamp
undershoot-protection circuit. When there is an
undershoot, the active-clamp circuit is enabled,
and current from VCC is supplied to clamp the
output, preventing the pass transistor from
turning on.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
NC – No internal connection
The device is organized as two 8-bit low-impedance switches with separate output-enable (OE) inputs. When OE is
low, the switch is on, and data can flow from the A port to the B port, or vice versa. When OE is high, the switch
is open, and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
SSOP – DL
40°C to 85°C
–40°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
TOP-SIDE
MARKING
Tube
SN74CBTK16245DL
Tape and reel
SN74CBTK16245DLR
Tape and reel
SN74CBTK16245DGGR
CBTK16245
CBTK16245
TVSOP – DGV
Tape and reel
SN74CBTK16245DGVR
CP245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
1A1
VCC
VCC
UC†
UC†
2
47
VCC
VCC
UC†
UC†
1B1
12
37
1A8
1B8
48
1OE
2A1
VCC
VCC
UC†
UC†
36
13
VCC
VCC
UC†
UC†
26
23
2A8
2B8
25
2OE
† Undershoot clamp
2
2B1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
5.5
VCC
VIH
Supply voltage
4
High-level control input voltage
2
VIL
TA
Low-level control input voltage
Operating free-air temperature
–40
UNIT
V
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP‡
MAX
UNIT
–1.2
V
–2
V
VIK
VIKU
VCC = 4.5 V,
VCC = 5.5 V,
II = –18 mA
0 mA ≥ II ≥ –50 mA,
II
VCC = 0,
VCC = 5.5 V,
VI = 5.5 V
VI = 5.5 V or GND
10
Ioff
ICC
VCC = 0,
VCC = 5.5 V,
VI or VO = 0 to 5.5 V
VI = VCC or GND,
20
VCC = 5.5 V,
VI = 3 V or 0
One input at 3.4 V,
VO = 3 V or 0,
VCC = 4 V,
TYP at VCC = 4 V
OE = VCC
∆ICC§
Ci
Cio(OFF)
Control inputs
Control inputs
ron¶
VCC = 4.5 V
OE = 5.5 V
±1
IO = 0
Other inputs at VCC or GND
µA
µA
3
µA
2.5
mA
3.5
pF
5.5
pF
VI = 2.4 V,
II = 15 mA
14
20
VI = 0
II = 64 mA
II = 30 mA
5
7
5
7
Ω
VI = 2.4 V,
II = 15 mA
8
12
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL-voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
FROM
(INPUT)
TO
(OUTPUT)
tpd†
A or B
B or A
0.35
ten
OE
A or B
7.4
PARAMETER
MAX
1.6
UNIT
MAX
0.25
ns
4.9
ns
tdis
A or B
7.4
4.2
7.5
ns
OE
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
undershoot characteristics
PARAMETER
TEST CONDITIONS
VOUTU
See Figures 1 and 2, and Table 1
‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
VCC
MIN
TYP‡
2
VOH–0.3
MAX
UNIT
V
VTR
R1
50 Ω
DUT
VIN
R2
10 pF
5.5 V
0V
–2 V
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage Waveform
Table 1. Device Test Conditions
PARAMETER
VALUE
B port under test§
See Figure 1
UNIT
VIN
tw
See Figure 2
V
20
ns
tr
tf
2
ns
2
ns
R1 = R2
100
kΩ
VTR
VCC
11
V
5.5
V
§ Other B-port outputs are open.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTK16245
16-BIT FET BUS SWITCH
WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS105D – APRIL 2000 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
tPLZ
3.5 V
1.5 V
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74CBTK16245DGGR
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
-40 to 85
CBTK16245
SN74CBTK16245DGVR
OBSOLETE
TVSOP
DGV
48
TBD
Call TI
Call TI
-40 to 85
CP245
SN74CBTK16245DL
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
-40 to 85
CBTK16245
SN74CBTK16245DLR
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
-40 to 85
CBTK16245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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