SN74CBTLV16292DLR

            


SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family 4-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Make-Before-Break Feature Internal 500-Ω Pulldown Resistors to Ground Latch-Up Performance Exceeds 250 mA Per JESD 17 S 1A NC 2A NC 3A NC GND 4A NC 5A NC 6A NC 7A NC VCC 8A GND NC 9A NC 10A NC 11A NC 12A NC description/ordering information The SN74CBTLV16292 is a 12-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. When the select (S) input is low, port A is connected to port B1, and RINT is connected to port B2. When S is high, port A is connected to port B2, and RINT is connected to port B1. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 NC NC 1B1 1B2 2B1 2B2 3B1 GND 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 GND 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 NC − No internal connection ORDERING INFORMATION SSOP − DL −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − DGG TOP-SIDE MARKING Tube SN74CBTLV16292DL Tape and reel SN74CBTLV16292DLR Tape and reel SN74CBTLV16292GR CBTLV16292 CBTLV16292 TVSOP − DGV Tape and reel SN74CBTLV16292VR CN292 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2003, Texas Instruments Incorporated   !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
            


SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 FUNCTION TABLE INPUT S FUNCTION L A port = B1 port RINT = B2 port H A port = B2 port RINT = B1 port logic diagram (positive logic) 54 2 1A 1B1 SW RINT RINT 53 SW 27 30 12B1 SW 12A 1B2 RINT RINT 29 12B2 SW 1 S 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
            


SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 UNIT V 1.7 V 2 0.7 0.8 V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
            


SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, ∆ICC‡ Control input Ci Control input VCC = 3.6 V, VI = 3.3 V or 0 Cio A or B port VO = 3.3 V or 0 TYP† Other inputs at VCC or GND MAX UNIT −1.2 V ±1 µA 10 µA 10 µA 300 µA 3.5 pF 22.5 VCC = 2.3 V, TYP at VCC = 2.5 V ron§ VCC = 3 V pF 5 8 VI = 0 II = 64 mA II = 24 mA 5 8 VI = 1.7 V, II = 15 mA 11 40 3 7 VI = 0 II = 64 mA II = 24 mA 3 7 Ω VI = 2.4 V, II = 15 mA 7 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A tpd# S A 2.5 7.1 ten tdis S B 1 5.6 PARAMETER MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 UNIT MAX 0.25 ns 2.5 6.7 ns 1 5 ns S B 1 5 1 4.5 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). # This propagation delay was measured by observing the change of voltage on the A output introduced by static levels equal to 3-V or 0 for 3.3 V ± 0.3 V or VCC or 0 for 2.5 V ± 0.2 V on B1 and B2 to achieve the desired transition. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER DESCRIPTION VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN tmbb|| Make-before-break time 0 2 0 2 || The make-before-break time is the time interval between make and break, during the transition from one selected port to the other. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX ns 
            


SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC Output Control Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 0V tPLZ tPZL VCC VCC/2 VOL + V∆ VOL tPHZ tPZH VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBTLV16292DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 SN74CBTLV16292DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 SN74CBTLV16292GR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 SN74CBTLV16292VR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CN292 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of