SN74CBTLV3125NSRG4

      

 SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 D Standard ’125-Type Pinout D 5-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4B 3OE 3A 3B 1 1A 1B 2OE 2A 2B DBQ PACKAGE (TOP VIEW) VCC 14 2 NC 1OE 1A 1B 2OE 2A 2B GND 14 2 13 4OE 3 12 4A 4 11 4B 5 10 3OE 9 3A 6 7 8 3B 1 Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II RGY PACKAGE (TOP VIEW) GND 1OE 1A 1B 2OE 2A 2B GND D 1OE D, DGV, NS, OR PW PACKAGE (TOP VIEW) D Ioff Supports Partial-Power-Down Mode 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4OE 4A 4B 3OE 3A 3B NC NC − No internal connection description/ordering information The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION QFN − RGY TOP-SIDE MARKING Tape and reel SN74CBTLV3125RGYR Tube SN74CBTLV3125D Tape and reel SN74CBTLV3125DR SOP − NS Tape and reel SN74CBTLV3125NSR CBTLV3125 SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3125DBQR CL125 TSSOP − PW Tape and reel SN74CBTLV3125PWR CL125 TVSOP − DGV Tape and reel SN74CBTLV3125DGVR SOIC − D −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA CL125 CBTLV3125 CL125 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated   !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 
      

 SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 FUNCTION TABLE (each bus switch) INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 3 2 1A 1OE 1B SW 1 6 5 2A 2B SW 4 2OE 9 8 3A 3B SW 10 3OE 12 11 4A SW 4B 13 4OE Pin numbers shown are for the D, DGV, NS, PW, and RGY packages. simplified schematic, each FET switch A B (OE) 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
      

 SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 UNIT V 1.7 V 2 0.7 0.8 V TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 
      

 SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ∆ICC‡ Control inputs Ci Control inputs Cio(OFF) VCC = 3.6 V, VI = 3 V or 0 TYP† MAX UNIT −1.2 V ±1 µA 10 µA 10 µA 300 µA 2.5 VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.5 V ron§ VCC = 3 V pF 7 pF 5 8 VI = 0 II = 64 mA II = 24 mA 5 8 VI = 1.7 V, II = 15 mA 27 40 5 7 VI = 0 II = 64 mA II = 24 mA 5 7 Ω VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A ten OE A or B 2 4.6 tdis OE A or B 1.1 3.9 PARAMETER MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 UNIT MAX 0.25 ns 2 4.4 ns 1 4.2 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
      

 SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input th VCC VCC/2 VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input 0V tPHL tPLH VCC/2 VCC/2 VOL tPLH tPHL Output Waveform 2 S1 at GND (see Note B) VOH Output VCC/2 VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V t Output PZL Waveform 1 S1 at 2 × VCC (see Note B) VOH Output VCC Output Control VCC/2 tPLZ VCC VCC/2 VOL + V∆ VOL tPHZ tPZH VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74CBTLV3125DBQRE4 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL125 Samples 74CBTLV3125DBQRG4 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL125 Samples 74CBTLV3125PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL125 Samples SN74CBTLV3125D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3125 Samples SN74CBTLV3125DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL125 Samples SN74CBTLV3125DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL125 Samples SN74CBTLV3125DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3125 Samples SN74CBTLV3125PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL125 Samples SN74CBTLV3125PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL125 Samples SN74CBTLV3125RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of