SN74CBTLV3126
SCDS038L – DECEMBER 1997 – REVISED AUGUST 2022
SN74CBTLV3126 Low-Voltage Quadruple FET Bus Switch
1 Features
3 Description
•
•
•
•
•
The SN74CBTLV3126 quadruple FET bus switch
features independent line switches. Each switch is
disabled when the associated output-enable (OE)
input is low.
Standard 126-type pinout
5-Ω switch connection between two ports
Rail-to-rail switching on data I/O ports
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 100 mA per JESD
78, Class II
2 Applications
•
•
•
•
•
Datacenter and enterprise computing
Broadband fixed line access
Building automation
Wired networking
Motor drives
This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device
when it is powered down. The SN74CBTLV3126
device has isolation during power off.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pull down resistor; the minimum value of the resistor
is determined by the current-sinking capability of the
driver.
Package Information(1)
PART NUMBER
SN74CBTLV3126
(1)
PACKAGE
BODY SIZE (NOM)
SOIC (D, 14)
8.65 mm × 3.91 mm
TVSOP (DGV, 14)
3.60 mm × 4.40 mm
TSSOP (PW, 14)
5.00 mm × 4.40 mm
VQFN (RGY, 14)
4.00 mm × 3.50 mm
SSOP (DBQ, 16)
4.90 mm × 3.90 mm
For all available packages, see the package option
addendum at the end of the data sheet.
SPACER
SPACER
A
B
(OE)
Simplified Schematic, Each FET Switch
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................8
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (June 2021) to Revision L (August 2022)
Page
• Updated the Overview section............................................................................................................................8
Changes from Revision J (January 2019) to Revision K (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed active low to active high in the Pin Configurations and Functions section to reflect logic description
change................................................................................................................................................................ 3
Changes from Revision I (October 2003) to Revision J (January 2019)
Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............ 1
• Added VIH MAX values in the Recommended Operating Conditions table........................................................ 5
2
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4OE
1B
3
12
4A
2OE
4
11
4B
2A
5
10
3OE
2B
6
9
3A
GND
7
8
3B
1A
2
1B
3
13
4OE
12
4A
11
4B
3OE
Th ermal
2OE
4
2A
5
10
2B
6
9
No t to scale
Figure 5-1. D, DGV, and PW Package, 14 Pin SOIC,
TVSOP, and TSSOP (Top View)
VCC
13
14
2
Pad
3A
8
1A
3B
VCC
1OE
14
7
1
GND
1OE
1
5 Pin Configuration and Functions
No t to scale
Figure 5-2. RGY Package, 14 Pin VQFN (Top View)
Table 5-1. Pin Functions, D, DGV, PW, RGY
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
1A
2
I/O
Channel 1 input or output
1B
3
I/O
Channel 1 input or output
1OE
1
I
Output enable, active high
2A
5
I/O
Channel 2 input or output
2B
6
I/O
Channel 2 input or output
2OE
4
I
Output enable, active high
3A
9
I/O
Channel 3 input or output
3B
8
I/O
Channel 3 input or output
3OE
10
I
Output enable, active high
4A
12
I/O
Channel 4 input or output
4B
11
I/O
Channel 4 input or output
4OE
13
I
Output enable, active high
GND
7
—
Ground
VCC
14
P
Power supply
—
Exposed thermal pad. There is no requirement to solder this pad; if connected, it should be left
floating or tied to GND.
Thermal Pad
(1)
I = input, O = output, I/O = input and output, P = power
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NC
1
16
VCC
1OE
2
15
4OE
1A
3
14
4A
1B
4
13
4B
2OE
5
12
3OE
2A
6
11
3A
2B
7
10
3B
GND
8
9
NC
No t to scale
Figure 5-3. DBQ Package, 16 Pin SSOP (Top View)
Table 5-2. Pin Functions, DBQ
PIN
NAME
TYPE(1)
DESCRIPTION
1A
3
I/O
Channel 1 input or output
1B
4
I/O
Channel 1 input or output
1OE
2
I
Output enable, active high
2A
6
I/O
Channel 2 input or output
2B
7
I/O
Channel 2 input or output
2OE
5
I
Output enable, active high
3A
11
I/O
Channel 3 input or output
3B
10
I/O
Channel 3 input or output
3OE
12
I
Output enable, active high
4A
14
I/O
Channel 4 input or output
4B
13
I/O
Channel 4 input or output
4OE
15
I
Output enable, active high
GND
8
—
Ground
NC
9
—
No internal connection
VCC
16
P
Power supply
(1)
4
NO.
I = input, O = output, I/O = input and output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
range(2)
–0.5
VI
Input voltage
II/O
Continuous channel current
IIK
Input clamp current
Tstg
Storage temperature range
(1)
(2)
VI/O < 0
–65
UNIT
V
4.6
V
128
mA
–50
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(1)
MIN
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
VCC
VCC = 2.7 V to 3.6 V
2
VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
–40
85
UNIT
V
V
V
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74CBTLV3126
THERMAL METRIC(1)
D
(SOIC)
DGV
(TVSOP)
PW
(TSSOP)
RGY
(VQFN)
DBQ
(SSOP)
UNIT
14 PINS
14 PINS
14 PINS
14 PINS
16 Pins
RθJA
Junction-to-ambient thermal resistance
100.6
154.8
123.3
59.6
118.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.5
64.5
53.0
71.3
66.4
°C/W
RθJB
Junction-to-board thermal resistance
56.8
88.4
66.3
35.6
62.2
°C/W
ΨJT
Junction-to-top characterization parameter
17.0
11.1
9.3
4.2
20.9
°C/W
ΨJB
Junction-to-board characterization parameter
56.4
87.4
65.7
35.7
61.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
16.1
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V,
II = –18 mA
II
VCC = 3.6 V,
Ioff
ICC
∆ICC
(2)
Ci
UNIT
V
VI = VCC or GND
±1
µA
VCC = 0,
VI or VO = 0 to 3.6 V
10
µA
10
µA
300
µA
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC or GND
Control
inputs
VI = 3 V or 0
VO = 3 V or 0,
OE = GND
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 0
ron (3)
VI = 1.7 V,
VI = 0
VCC = 3 V
VI = 2.4 V,
(1)
(2)
(3)
MAX
–1.2
Control
inputs
Cio(OFF)
TYP(1)
MIN
2.5
pF
7
pF
II = 64 mA
5
II = 24 mA
5
8
8
II = 15 mA
27
40
II = 64 mA
5
7
II = 24 mA
5
7
II = 15 mA
10
15
Ω
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
(1)
6
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
ten
OE
A or B
1.6
4.5
tdis
OE
A or B
1.3
4.7
PARAMETER
MIN
MAX
MIN
0.15
UNIT
MAX
0.25
ns
1.9
4.2
ns
1
4.8
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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7 Parameter Measurement Information
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
2.5 V ±0.2 V
3.3 V ±0.3 V
30 pF
50 pF
500 Ω
500 Ω
0.15 V
0.3 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
A.
B.
C.
D.
E.
F.
G.
H.
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
0V
t
Output PZL
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC
Output
Control
tPLZ
VCC/2
VCC
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
The outputs are measured one at a time with one transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low. This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when
it is powered down. The SN74CBTLV3126 device has isolation during power off. To ensure the high-impedance
state during power up or power down, OE should be tied to GND through a pull down resistor; the minimum
value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
A
B
(OE)
8.3 Feature Description
The SN74CBTLV3126 features 5-Ω switch connection between ports, allowing for low signal loss across the
switch. Rail-to-rail switching on data I/O allows for full voltage swing outputs. Ioff supports partial-power-down
mode operation, protecting the chip from voltages at output ports when it is not powered on. Latch-up
performance exceeds 100 mA per JESD 78, Class II.
8.4 Device Functional Modes
8.4.1 Function Table (Each Bus Switch)
Table 8-1 provides the truth table for the SN74CBTLV3126.
Table 8-1. Truth Table
INPUT
OE
8
FUNCTION
L
Disconnect
H
A port = B port
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2
1A
3
1B
SW
1
1OE
5
2A
6
2B
SW
4
2OE
9
3A
8
3B
SW
10
3OE
12
4A
11
SW
4B
13
4OE
Figure 8-1. Logic Diagram (Positive Logic)
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
One useful application to take advantage of the SN74CBTLV3126 features is isolating various protocols from
a possessor or MCU such as JTAG, SPI, or standard GPIO signals. The device provides excellent isolation
performance when the device is powered. The added benefit of powered-off protection allows a system to
minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
9.2 Typical Application
9.2.1 Protocol and Signal Isolation
VDD
VDD
0.1 µF
Processor
JTAG, SPI, GPIO
Port
TDI / CIPO / GPIO
TDO / COPI / GPIO
TCK / SCLK / GPIO
TMS / SS / GPIO
VI/O
FLASH
S1
D1
S2
D2
S3
D3
S4
JTAG
DEBUG,
SPI, GPIO
RAM
CPU
D4
GND
SEL1
SEL2
SEL3
SEL4
1.8 V
Logic I/O
Peripherals
GND
Figure 9-1. Typical Appliction
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
10
VALUES
Supply (VDD)
3.3 V
Input or output signal range
0 V to 3.3 V
Control logic thresholds
1.8 V compatible
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9.2.1.2 Detailed Design Procedure
The SN74CBTLV3126 can operate without any external components except for the supply decoupling
capacitors. TI recommends that the digital control pins (OE) be pulled up to VCC or down to GND to avoid
an undesired switch state that could result from the floating pin. All input signals passing through the switch must
fall within the Recommend Operating Conditions of the SN74CBTLV3126 including signal range and continuous
current. For this design example, with a supply of 3.3 V, the signals can range from 0 V to 3.3 V when the device
is powered. This example can also utilize the Powered-off Protection feature, and the inputs can range from 0 V
to 3.3 V when VDD = 0 V.
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, a 0.1-μF bypass capacitor is recommended. If multiple pins
are labeled VCC, then a 0.01-μF or 0.022-μF capacitor is recommended for each VCC because the VCC pins are
tied together internally. For devices with dual supply pins operating at different voltages, for example VCC and
VDD, a 0.1-μF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise, use
multiple bypass capacitors in parallel. Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel.
The bypass capacitor should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight, and therefore; some traces must
turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 11-1. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-hole
pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
• Avoid stubs on the high-speed signals traces because they cause signal reflections.
• Route all high-speed signal traces over continuous GND planes, with no interruptions.
• Avoid crossing over anti-etch, commonly found with plane splits.
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•
When working with high frequencies, a printed circuit board with at least four layers is recommended; two
signal layers separated by a ground and power layer as shown in Figure 11-2.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 11-2. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer
must be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or
power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing
the number of signal vias reduces EMI by reducing inductance at high frequencies.
Figure 11-3 shows an example of a PCB layout with the SN74CBTLV3126. Some key considerations are:
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
trace for power
Via to G ND plane
C
1OE
VCC
1A
4OE
1B
4A
2OE
SN74CBTLV312 6
4B
2A
3OE
2B
3A
GND
3B
Figure 11-3. Example Layout
12
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74CBTLV3126
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74CBTLV3126RGYRG4
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL126
Samples
SN74CBTLV3126D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3126
Samples
SN74CBTLV3126DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL126
Samples
SN74CBTLV3126DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL126
Samples
SN74CBTLV3126DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3126
Samples
SN74CBTLV3126PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL126
Samples
SN74CBTLV3126PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL126
Samples
SN74CBTLV3126RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL126
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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