SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003
D 5-Ω Switch Connection Between Two Ports
D Rail-to-Rail Switching on Data I/O Ports
D Ioff Supports Partial-Power-Down Mode
D
D
DBQ, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
Operation
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description/ordering information
The SN74CBTLV3861 provides ten bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NC − No internal connection
The device is organized as one 10-bit bus switch.
When output enable (OE ) is low, the 10-bit bus
switch is on, and port A is connected to port B.
When OE is high, the switch is open, and the
high-impedance state exists between the two
ports.
This device is fully specified for partial-power-down applications using I off. The I off feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tape and reel
SN74CBTLV3861DBQR
CBTLV3861
Tube
SN74CBTLV3861DW
Tape and reel
SN74CBTLV3861DWR
SOP − NS
Tape and reel
SN74CBTLV3861NSR
CBTLV3861
TSSOP − PW
Tape and reel
SN74CBTLV3861PWR
CL861
TVSOP − DGV
Tape and reel
SN74CBTLV3861DGVR
PACKAGE†
TA
QSOP − DBQ
SOIC − DW
−40°C to 85°C
CBTLV3861
CL861
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+$ ,#$(!,'&$% &!" $ %)(&$% )(! $.( $(!"% (/#% %$!'"($%
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1
SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
A1
22
B1
SW
11
A10
13
SW
B10
23
OE
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
2.3
3.6
1.7
UNIT
V
V
2
0.7
0.8
V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II
VCC = 3 V,
VCC = 3.6 V,
II = −18 mA
VI = VCC or GND
Ioff
ICC
VCC = 0,
VCC = 3.6 V,
VI or VO = 0 to 3.6 V
IO = 0,
VCC = 3.6 V,
VI = 3 V or 0
One input at 3 V,
VO = 3 V or 0,
OE = VCC
∆ICC‡
Ci
Control inputs
Control inputs
Cio(OFF)
MIN
TYP†
VI = VCC or GND
Other inputs at VCC or GND
MAX
−1.2
V
±1
µA
10
µA
10
µA
300
µA
3
VI = 0
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 1.7 V,
ron§
VI = 0
VCC = 3 V
UNIT
pF
5
pF
II = 64 mA
II = 24 mA
5
8
5
8
II = 15 mA
II = 64 mA
27
40
5
7
Ω
II = 24 mA
5
7
VI = 2.4 V,
II = 15 mA
10
15
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
ten
OE
A or B
2.1
5.5
OE
A or B
1.7
5.5
PARAMETER
tdis
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
2.1
4.9
ns
2.5
5.8
ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
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3
SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
RL
From Output
Under Test
S1
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
CL
30 pF
50 pF
VCC
2.5 V ±0.2 V
3.3 V ±0.3 V
LOAD CIRCUIT
V∆
0.15 V
0.3 V
RL
500 Ω
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
0V
t
Output PZL
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VOH
Output
VCC
Output
Control
tPLZ
VCC
VCC/2
tPZH
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74CBTLV3861DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CBTLV3861
SN74CBTLV3861DGVR
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL861
SN74CBTLV3861DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3861
SN74CBTLV3861DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3861
SN74CBTLV3861NSR
ACTIVE
SO
NS
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3861
SN74CBTLV3861PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL861
SN74CBTLV3861PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL861
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of