SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
D
D
D
D, DB, OR N PACKAGE
(TOP VIEW)
Internal Look-Ahead Circuitry for Fast
Counting
Carry Output for N-Bit Cascading
Fully Synchronous Operation for Counting
CLR
CLK
A
B
C
D
ENP
GND
description
1
16
2
15
3
14
4
13
5
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
12
This synchronous, presettable, 4-bit binary
6
11
counter has internal carry look-ahead circuitry
7
10
for use in high-speed counting designs.
8
9
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop
outputs to low, regardless of the levels of CLK, LOAD, ENP, and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
0°C to 70°C
SOIC – D
SSOP – DB
ORDERABLE
PART NUMBER
Tube
SN74F161AN
Tube
SN74F161AD
Tape and reel
SN74F161ADR
Tape and reel
SN74F161ADBR
TOP-SIDE
MARKING
SN74F161AN
F161A
F161A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
state diagram
0
2
3
4
15
5
14
6
13
7
12
2
1
11
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9
• DALLAS, TEXAS 75265
8
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic diagram (positive logic)
CLR
LOAD
ENT
ENP
1
9
10
15
7
RCO
R
14
CLK
A
2
3
G2
QA
1, 2T/C3
1, 3D
M1
R
13
G2
QB
1, 2T/C3
B
4
1, 3D
M1
R
12
G2
QC
1, 2T/C3
C
5
1, 3D
M1
R
11
G2
QD
1, 2T/C3
D
6
1, 3D
M1
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3
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic symbol, each flip-flop
R
TE
R
Q1
1, 2T/C3
CLK
D
Q1
G2
Q2
1, 3D
Q2
LOAD
M1
logic diagram, each flip-flop (positive logic)
R
TE
(Toggle
Enable)
Q1
CLK
Q2
D
LOAD
4
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SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Data
Outputs
QB
QC
QD
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
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5
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
V
Input clamp current
–18
mA
IOH
IOL
High-level output current
–1
mA
Low-level output current
20
mA
High-level input voltage
2
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 1 mA
VCC = 4.75 V,
VCC = 4.5 V,
IOH = – 1 mA
IOL = 20 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
MIN
2.5
TYP‡
ENT, LOAD
0.3
V
0.5
V
0.1
mA
20
µA
– 0.6
VCC = 5.5 V,
VI = 0.5 V
– 1.2
mA
– 0.6
VCC = 5.5 V,
VCC = 5.5 V
VO = 0
– 60
37
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
6
V
2.7
CLR
IOS§
ICC
UNIT
– 1.2
3.4
ENP, CLK, A, B, C, D
IIL
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–150
mA
55
mA
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
fclock
Clock frequency
CLK high or low (loading)
tw
Pulse duration
CLK (counting)
tsu
ENP and ENT before CLK↑
Data after CLK↑
th
Hold time
LOAD after CLK↑
ENP and ENT after CLK↑
tsu
Inactive-state setup time, CLR high before CLK↑†
† Inactive-state setup time also is referred to as recovery time.
0
100
MIN
0
5
5
4
4
Low
6
7
5
5
High or low
LOAD before CLK↑
Setup time
MAX
High
CLR low
Data before CLK↑
MIN
5
5
High
11
11.5
Low
8.5
9.5
High
11
11.5
Low
5
5
High or low
2
2
High
2
2
Low
0
0
High or low
0
0
6
6
MAX
UNIT
90
MHz
ns
ns
ns
ns
switching characteristics (see Note 4)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V TO 5.5 V,
CL = 50 PF,
RL = 500 Ω,
TA = MIN TO MAX‡
MIN
MAX
100
120
2.7
5.1
7.5
2.7
8.5
2.7
7.1
10
2.7
11
3.2
5.6
8.5
3.2
9.5
3.2
5.6
8.5
3.2
9.5
4.2
9.6
14
4.2
15
4.2
9.6
14
4.2
15
1.7
4.1
7.5
1.7
8.5
1.7
4.1
7.5
1.7
8.5
Any Q
4.7
8.6
12
4.7
13
RCO
3.7
7.6
10.5
3.7
11.5
CLK (LOAD high)
Any Q
CLK (LOAD low)
Any Q
CLK
RCO
ENT
RCO
CLR
VCC = 5 V,
CL = 50 PF,
RL = 500 Ω,
TA = 25°C
MIN
TYP
MAX
90
UNIT
MHz
ns
ns
ns
ns
ns
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 4: Load circuits and waveforms are shown in Figure 1.
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• DALLAS, TEXAS 75265
7
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
From Output
Under Test
CL
(see Note A)
Test
Point
500 Ω
7V
Open
500 Ω S1
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
Open
7V
Open
7V
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
VOH
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
1.5 V
VOL
1.5 V
0V
tPZL
tPLZ
≈3.5 V
1.5 V
tPZH
tPLH
1.5 V
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74F161AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
F161A
Samples
SN74F161ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
F161A
Samples
SN74F161AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74F161AN
Samples
SN74F161ANSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
74F161A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of