SN74F169N


   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 • • • • • D OR N PACKAGE (TOP VIEW) Fully Synchronous Operation for Counting and Programming Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Independent Clock Circuit Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs U/D CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD description This synchronous, presettable, 4-bit up/down binary counter features an internal carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. This counter is fully programmable; that is, it may be preset to any number between 0 and its maximum count. The load-input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and a ripple-carry (RCO) output. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. Input ENT is fed forward to enable the RCO. RCO thus enabled will produce a low-level pulse while the count is zero (all inputs low) counting down or maximum (9 or 15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. The SN74F169 features a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD or U/D) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the setup and hold times. The SN74F169 is characterized for operation from 0°C to 70°C. Copyright  1993, Texas Instruments Incorporated      !"# $ %&'# "$  (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$, • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2−1 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 logic symbol† 9 LOAD 1 U/D 10 ENT ENP CLK 7 2 CTRDIV16 M1 [LOAD] M2 [COUNT] M3 [UP] M4 [DOWN] 3,5CT = 15 4,5CT = 0 G5 15 RCO G6 2,3,5,6+/C7 2,4,5,6 − A B C D 3 1 1, 7D 4 2 5 4 6 8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 14 13 12 11 QA QB QC QD 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 logic diagram (positive logic) LOAD U/D ENT ENP 9 1 10 7 15 CLK A RCO 2 G2 1, 2T/C3 1, 3D 3 14 QA M1 B G2 1, 2T/C3 1, 3D 4 13 QB M1 C G2 1, 2T/C3 1, 3D 5 12 QC M1 D G2 1, 2T/C3 1, 3D 6 11 QD M1 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−3 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 logic symbol, each flip-flop TE G2 Q1 Q2 1, 2T/C3 CLK DATA 1, 3D Q1 LOAD M1 Q2 logic diagram, each flip-flop (positive logic) TE (Toggle Enable) CLK Q1 Q2 DATA LOAD Q1 Q2 FUNCTION TABLE (each flip-flop) COUNTER INPUTS 2−4 LOAD CLK L L FLIP-FLOP INPUTS LOAD TE ↑ H ↑ H H ↑ H ↑ OUTPUTS CLK DATA Q L ↓ H H L L ↓ L L H L H ↓ X Q0 Q0 L L ↓ X Q0 Q0 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Q 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 typical load, count, and inhibit sequences Illustrated below is the following sequence: 1. Load (preset) to binary thirteen 2. Count up to fourteen, fifteen (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen LOAD A Data Inputs B C D CLK U/D ENP and ENT QA Data Outputs QB QC QD RCO 13 14 15 0 1 2 Count Up 2 2 Inhibit 1 0 15 14 13 Count Down Load • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−5 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 V Input clamp current −18 mA IOH IOL High-level output current −1 mA Low-level output current 20 mA TA Operating free-air temperature 70 °C High-level input voltage 2 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = − 18 mA IOH = − 1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = − 1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V ENT IIL All others MIN TYP‡ 2.5 3.4 MAX UNIT −1.2 V V 2.7 0.3 0.5 V 0.1 mA 20 µA − 1.2 VCC = 5.5 V, VI = 0.5 V − 0.6 mA IOS§ VCC = 5.5 V, VO = 0 −60 −150 mA ICC VCC = 5.5 V, See Note 2 38 52 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with B and ENT inputs high and all other inputs low. 2−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C fclock tw tsu Clock frequency Pulse duration CLK high or low Setup time Hold time MAX 0 100 MIN MAX UNIT 0 90 MHz 5 5.5 Data before CLK↑ High or low 4 4.5 LOAD before CLK↑ High or low 8 9 ENP and ENT before CLK↑ High or low 5 6 High 11 12.5 U/D before CLK↑ th MIN Low 7 8 Data after CLK↑ High or low 3 3.5 LOAD after CLK↑ High or low 0 0 ENP and ENT after CLK↑ High or low 0 0 U/D after CLK↑ High or low 0 0 ns ns ns switching characteristics (see Note 3) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH FROM (INPUT) TO (OUTPUT) CLK Q CLK RCO ENT RCO U/D RCO VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† MIN TYP 100 115 MAX MIN 2.2 6.1 8.5 2.2 9.5 3.2 8.6 11.5 3.2 13 4.7 11.6 15.5 4.7 17 3.2 8.1 11 3.2 12.5 1.7 4.1 6 1.7 7 1.7 5.6 8 1.7 9 2.7 8.1 11 2.7 12.5 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • MAX 90 tPHL 3.2 7.6 10.5 3.2 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. UNIT MHz 12 ns ns ns ns 2−7 

   
     SDFS089 − MARCH 1987 − REVISED OCTOBER 1993 2−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 6-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74F169D OBSOLETE SOIC D 16 TBD Call TI Call TI 0 to 70 F169 SN74F169N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74F169N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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