SN74F175DR

SN74F175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SDFS058B – D293, MARCH 1987 – REVISED MAY 2002 D D D D, N, OR NS PACKAGE (TOP VIEW) Contains Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators CLR 1Q 1Q 1D 2D 2Q 2Q GND description This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR) input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4Q 4Q 4D 3D 3Q 3Q CLK ORDERING INFORMATION PDIP – N 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – D Tube SN74F175N Tube SN74F175D Tape and reel SN74F175DR TOP-SIDE MARKING SN74F175N F175 SOP – NS Tape and reel SN74F175NSR 74F175 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OUTPUTS CLR CLK D Q Q L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74F175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SDFS058B – D293, MARCH 1987 – REVISED MAY 2002 logic diagram (positive logic) CLK CLR 1D 9 1 4 1D 2 1Q C1 3 R 1Q Two Identical Channels Not Shown 4D 13 1D 15 4Q C1 R 14 4Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input voltage ratings may be exceeded if the input current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 V Input clamp current –18 mA IOH IOL High-level output current –1 mA Low-level output current 20 mA High-level input voltage 2 V V TA Operating free-air temperature 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74F175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SDFS058B – D293, MARCH 1987 – REVISED MAY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS‡ ICC TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = –1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, MIN 2.5 TYP† MAX UNIT –1.2 V 3.4 V 2.7 0.3 0.5 V VI = 7 V VI = 2.7 V 0.1 mA 20 µA VI = 0.5 V VO = 0 – 0.6 mA –150 mA –60 VCC = 5.5 V, See Note 4 22.5 34 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 4: ICC is measured with outputs open, with 4.5 V applied to all data inputs after a momentary ground, followed by 4.5 V applied to CLK. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C MIN fclock tw tsu Clock frequency MIN 100 CLK high 4 4 CLK low 5 5 CLR low 5 5 Setup time, data before CLK↑ High or low 3 3 Setup time, inactive state, data before CLK↑§ CLR high 5 5 1 1 Pulse duration th Hold time, data after CLK↑ High or low § Inactive-state setup time also is referred to as recovery time. MAX UNIT 100 MHz MAX ns ns ns switching characteristics (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) CLK CLR TO (OUTPUT) VCC = 5 V, TA = 25°C VCC = 4.5 V to 5.5 V TYP 100 140 3.2 4.6 6.5 3.2 7.5 3.2 6.1 8.5 3.2 9.5 Q 3.2 6.1 8.5 3.2 9 Q 3.7 8.6 11.5 3.7 13 Q or Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX MIN UNIT MIN MAX 100 MHz ns ns 3 SN74F175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SDFS058B – D293, MARCH 1987 – REVISED MAY 2002 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL (see Note A) 500 Ω S1 From Output Under Test Test Point CL (see Note A) 500 Ω Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 7V Open Collector LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V 1.5 V Data Input 0V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL 1.5 V VOH 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLH 1.5 V 3V Output Control tPZL VOH In-Phase Output Out-of-Phase Output 0V VOLTAGE WAVEFORMS PULSE DURATION tPLZ 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS ≈3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns, duty cycle = 50%. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74F175D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 F175 SN74F175DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 F175 SN74F175N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74F175N SN74F175NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74F175 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of