SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
D
D
D
D
Compatible With IEEE Std 1194.1-1991
(BTL)
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
Open-Collector B-Port Outputs Sink
100 mA
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion/Withdrawal
D
D
D
High-Impedance State During Power Up
and Power Down
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
AI2
AO1
AI1
GND
VCC
CLKAB/LEAB
IMODE1
IMODE0
BG VCC
OEA
BG GND
BIAS VCC
B1
RC PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
B8
OEB
OEB
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
AO7
AI8
AO8
GND
VCC
CLKBA/LEBA
OMODE0
OMODE1
VCC
GND
AO2
AI3
AO3
AI4
AO4
LOOPBACK
AI5
AO5
AI6
AO6
AI7
GND
description
The SN74FB2033K is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port.
The common I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The
SN74FB2033K is specifically designed to be compatible with IEEE Std 1194.1-1991.
The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for
B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured
in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock
inputs serve as active-high transparent latch enables.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
description (continued)
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (before inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.5 V, the
AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
The B port is controlled by OEB and OEB. If OEB is low, or OEB is high, or when VCC is less than 2.5 V, the B port
is inactive. If OEB is high and OEB is low, the B port is active.
BG VCC and BG GND are the bias-generator reference inputs.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO port) or inactive (B port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing
effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V.
Both of these clamps are active only during ac switching and do not affect the BTL outputs during steady-state
conditions.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C QFP – RC Tube
SN74FB2033KRC
FB2033K
† Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
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SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
Function Tables
FUNCTION
INPUTS
FUNCTION/MODE
OEA
OEB
OEB
OMODE1
OMODE0
IMODE1
IMODE0
LOOPBACK
L
L
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
H
L
L
L
X
X
X
AI to B, buffer mode
X
H
L
L
H
X
X
X
AI to B, flip-flop mode
X
H
L
H
X
X
X
X
AI to B, latch mode
H
L
X
X
X
L
L
L
H
X
H
X
X
L
L
L
H
L
X
X
X
L
H
L
H
X
H
X
X
L
H
L
H
L
X
X
X
H
X
L
H
X
H
X
X
H
X
L
H
L
X
X
X
L
L
H
H
X
H
X
X
L
L
H
H
L
X
X
X
L
H
H
H
X
H
X
X
L
H
H
H
L
X
X
X
H
X
H
H
X
H
X
X
H
X
H
H
H
L
X
X
X
X
L
Isolation
B to
t AO
AO, b
buffer
ff mode
d
B to
t AO,
AO flip-flop
fli fl mode
d
B to
t AO
AO, llatch
t h mode
d
AI to AO
AO, buffer mode
AI to AO,
AO flip-flop
flip flop mode
AI to AO,
AO latch mode
AI to B, B to AO
ENABLE/DISABLE
INPUTS
OEA
OEB
OUTPUTS
OEB
AO
B
L
X
X
Hi Z
H
X
X
Active
X
L
L
Inactive (H)
X
L
H
Inactive (H)
X
H
L
Active
X
H
H
Inactive (H)
BUFFER
INPUT
OUTPUT
L
H
H
L
LATCH
INPUTS
CLK/LE
DATA
OUTPUT
H
L
H
H
H
L
L
X
Q0
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3
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
Function Tables (Continued)
LOOPBACK
LOOPBACK
Q†
L
B port
Point P‡
H
† Q is the input to the B-to-A
logic element.
‡ P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
MODE1
SELECTED-LOGIC
ELEMENT
MODE0
L
L
Buffer
L
H
Flip-flop
H
X
Latch
FLIP-FLOP
INPUTS
4
CLK/LE
DATA
OUTPUT
L
X
Q0
↑
L
H
↑
H
L
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SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
functional block diagram
23
OEB
OEB
OMODE1
24
21
20
OMODE0
47
CLKAB/ LEAB
Transceiver
1D
C1
40
AI1
B1
50
P
1D
C1
IMODE1
46
45
IMODE0
19
CLKBA/ LEBA
1D
C1
51
Q
AO1
OEA
1D
43
C1
One of Eight Channels
LOOPBACK
7
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5
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V
Voltage range applied to any output in the high state, VO: A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC
Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V
Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC, BG VCC
BIAS VCC
Supply voltage
4.75
5
5.25
V
Supply voltage
4.5
5
5.5
V
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IOH
High-level output current
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
B port
Except B port
B port
1.62
2.3
2
0.75
1.47
Except B port
0.8
AO port
–3
AO port
B port
Except B port
24
100
10
V
V
mA
mA
ns/V
TA
Operating free-air temperature
0
70
°C
NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to VCC(5 V) or GND, and
B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
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SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
B port
Except B port
AO port
TEST CONDITIONS
VCC = 4.75 V,
VCC = 4.75 V,
II = –18 mA
II = –40 mA
VCC = 4.75 V to 5.25 V,
IOH = –10 µA
IOH = –3 mA
VCC = 4
4.75
75 V
AO port
IOH = –32 mA
IOL = 20 mA
75 V
VCC = 4
4.75
IOL = 55 mA
IOL = 100 mA
VOL
B portt
VCC = 4
4.75
75 V
II
Except B port
IIH
Except B port
B port‡
VCC = 0,
VCC = 5.25 V,
IIL
Except B port
B port‡
IOL = 4 mA
VI = 5.25 V
VCC = 0 to 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 0 to 5.25 V,
IOH
IOZH
B port
IOZL
IOZPU
AO port
IOZPD
IOS§
A port
ICC
Ci
All outputs on
Co
AO port
VI = 0.5 V or 2.5 V
VO = 0.5 V or 2.5 V
Ciio
B port
per IEEE Std 1194.1-1991
VCC = 0 to 4.75 V
VCC = 4.75 V to 5.25 V
AO port
VCC = 2.1 V to 5.25 V,
VCC = 2.1 V to 5.25 V,
A port
VCC = 0 to 2.1 V,
VCC = 2.1 V to 0,
AO port
AI port and control inputs
VCC = 5.25 V,
VCC = 5.25 V,
MIN
TYP†
MAX
–1.2
–0.5
2.5
2.85
VCC–1.1
3.4
0.33
0.5
UNIT
V
V
2
0.8
0.75
1.1
V
0.5
100
VI = 2.7 V
VI = 2.1 V
50
100
VI = 0.5 V
VI = 0.75 V
–100
–50
µA
µA
µA
VO = 2.1 V
VO = 2.7 V
100
µA
50
µA
VO = 0.5 V
VO = 0.5 V to 2.7 V
–50
µA
50
µA
VO = 0.5 V to 2.7 V
VO = 0
–50
µA
–80
–150
mA
45
70
mA
–40
IO = 0
5
pF
5
pF
6
6
pF
† All typical values are at VCC = 5 V, TA = 25°C
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
live-insertion characteristics over recommended operating free-air temperature range (see Note 3)
PARAMETER
ICC (BIAS VCC)
VO
IO
B port
B port
TEST CONDITIONS
VCC = 0 to 4.75 V,
VCC = 4.75 V to 5.25 V,
VB = 0 to 2 V,
VB = 0 to 2 V,
VCC = 0,
VCC = 0,
BIAS VCC = 5 V
VCC = 0 to 5.25 V,
VCC = 0 to 2.2 V,
MIN
BIAS VCC = 4.5 V to 5.5 V
BIAS VCC = 4.5 V to 5.5 V
1.62
VB = 1 V,
OEB = 0 to 0.8 V
VI (BIAS VCC) = 4.75 V to 5.25 V
OEB = 0 to 5 V
MAX
UNIT
1.2
mA
10
µA
2.1
V
100
µA
–1
100
NOTE 3: Power-up sequence is GND, BIAS VCC, VCC.
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7
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
VCC = 5 V,
TA = 25°C
8
MIN
MAX
0
150
MIN
MAX
UNIT
0
150
MHz
fclock
tw
Clock frequency
Pulse duration, CLKAB/LEAB or CLKBA/LEBA
3.3
3.3
ns
tsu
th
Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑
2.7
2.7
ns
Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑
0.7
0.7
ns
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SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
FROM
(INPUT)
PARAMETER
fmax
tPLH
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
MIN
150
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
AI (through mode)
B
B (through
(th
h mode)
d )
AO
AI (transparent)
B
B (transparent)
(t
t)
AO
OEB
B
OEB
B
OEA
AO
OEA
AO
CLKAB/LEAB
B
CLKBA/LEBA
AO
OMODE
B
IMODE
AO
LOOPBACK
AO
AI
AO
tPHL
tr
Rise time, 1.3 V to 1.8 V, B port
MAX
UNIT
MAX
150
MHz
2.8
5.1
6.8
2.8
8.1
2.5
4.2
5.7
2.5
6.1
3.1
4.3
5.1
2.2
6.6
3.1
4.2
5.1
2.6
6
2.8
5.1
6.8
2.8
8.1
2.6
4.2
5.7
2.6
6.1
2.2
4.3
6
2.2
6.6
2.5
4.2
5.6
2.5
6
2.7
5.1
6.8
2.7
8.3
2.4
4.2
5.7
2.4
6.1
2.5
4.8
6.4
2.5
7.7
2.5
4.3
5.9
2.5
6.4
1.6
3.6
5.1
1.6
5.6
2.3
4.3
5.7
2.3
6
1.7
4
5.5
1.7
5.9
1.2
2.9
4.4
1.2
4.7
5.2
6.5
7.8
3.7
9.9
3.8
5.4
7.1
3.4
7.7
1.7
3.8
5.5
1.7
5.9
1.8
3.6
5.1
1.8
5.5
2.9
6.6
8.4
2.9
10
3
5.7
7.5
3
8.3
1.4
4.1
5.8
1.4
6.4
1.9
4.2
5.7
1.9
5.9
2
5.2
7.3
2
8.2
2.6
4.8
6.3
2.6
6.4
1.7
3.9
5.6
1.7
6.1
2.2
4.3
5.7
2.2
5.9
1.8
2.5
3.8
1.7
4
tf
tr
Fall time, 1.8 V to 1.3 V, B port
1.7
2.5
3.8
1.5
4
Rise time, 10% to 90%, AO
2.5
3.4
4.8
2
5
tf
Fall time, 90% to 10%, AO
1.5
2.5
3.8
1
5
1
B-port input pulse rejection
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
output-voltage characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
Peak output voltage during turnoff of 100 mA into 40 nH
B port
See Figure 1
Minimum output voltage during turnoff of 100 mA into 40 nH
B port
See Figure 1
1.62
V
VOLV
Minimum output voltage during high-to-low switch
B port
IOL = –50 mA
0.3
V
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3
UNIT
VOHP
VOHV
V
9
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
40 nH
9Ω
30 pF
Figure 1. Load Circuit for VOHP and VOHV
10
POST OFFICE BOX 655303
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SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
2.1 V
9Ω
7V
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
S1
Open
Test
Point
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR A OUTPUTS
S1
Open
7V
Open
LOAD CIRCUIT FOR B OUTPUTS
3V
Timing Input
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
tw
1.5 V
3V
0V
Input
tsu
1.5 V
0V
th
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Data Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Control
1.5 V
1.5 V
0V
3V
Input
1.5 V
tPZL
1.5 V
0V
tPHL
tPLH
1.55 V
1.55 V
VOH
Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
2.1 V
Input
1.55 V
1.55 V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
3.5 V
1.5 V
VOL + 0.3 V
VOL
tPZH
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOH
VOH – 0.3 V
1.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A PORT)
1V
tPHL
tPLH
VOHP
VOHV
VOH
Output
1.5 V
1.5 V
VOLV
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
2.1 V
1V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Orderable Device
SN74FB2033KRC
Status
(1)
ACTIVE
Package Type Package
Drawing
QFP
RC
Pins
Package Qty
52
96
Eco Plan
TBD
(2)
Lead/
Ball Finish
CU SNPB
MSL Peak Temp
(3)
Samples
(Requires Login)
Level-2-240C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
MECHANICAL DATA
MQFP003 – OCTOBER 1994
RC (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
0,65
39
0,13 M
27
40
26
52
14
0,16 NOM
1
13
7,80 TYP
10,20
SQ
9,80
13,45
SQ
12,95
Gage Plane
0,25
0,05 MIN
2,20
1,80
0°– 7°
1,03
0,73
Seating Plane
2,45 MAX
0,10
4040151 / B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
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