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SN74GTL2014
SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014
SN74GTL2014 4-Channel LVTTL to GTL Transceiver
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
Operates as a GTL–/GTL/GTL+ to LVTTL or
LVTTL to GTL–/GTL/GTL+ Translator
The LVTTL Inputs are Tolerant up to 5.5 V
Allowing Direct Access to TTL or 5 V CMOS
The GTL Input/Output Operate up to 3.6 V,
Allowing the Device to be Used in High Voltage
Open-Drain Applications
VREF Goes Down to 0.5 V for Low Voltage CPU
Usage
Partial Power-Down Permitted
Latch-up Protection Exceed 500 mA per JESD78
Package Option: TSSOP14
–40°C to 85°C Operating Temperature Range
ESD Protection on All Terminals
– 2000 V HBM, JESD22-A114
– 1000 V CDM, IEC61000-4-2
Server
Base Station
Wireline Communication
3 Description
The SN74GTL2014 is a 4-channel translator to
interface between 3.3-V LVTTL chip set I/O and Xeon
processor GTL–/GTL/GTL+ I/O.
The SN74GTL2014 integrates ESD protection cells
on all terminals and is available in a TSSOP package
(5.0 mm × 4.4 mm). The device is characterized over
the free air temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
SN74GTL2014
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
GTL2014
B0
+
–
A0
B1
+
–
A1
B2
+
–
A2
B3
+
–
A3
002aab139
VREF
DIR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74GTL2014
SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Electrical Characteristics............................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Trademarks ........................................................... 13
12.2 Electrostatic Discharge Caution ............................ 13
12.3 Glossary ................................................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
Changes from Original (February 2014) to Revision A
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
•
Updated Specifications section .............................................................................................................................................. 4
•
Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ......................................................................................... 9
•
Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ....................................................................................... 11
•
Added Power Supply Recommendations ............................................................................................................................ 12
2
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SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014
5 Pin Configuration and Functions
TSSOP Package (14 Pin)
(Top View)
DIR
1
14 VCC
B0
2
13 A0
B1
3
12 A1
VREF
4
B2
5
10 A2
B3
6
9
A3
GND
7
8
GND
GTL2014
11 GND
Pin Functions
PIN
NAME
DESCRIPTION
NUMBER
A0
13
A01
12
A02
10
A03
9
B0
2
B01
3
B02
5
B03
6
DIR
1
LVTTL data input/output
GTL data input/output
Direction control input (LVTTL)
7
GND
8
Ground
11
VCC
14
Supply voltage
VREF
4
GTL reference voltage
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6 Specifications
6.1 Absolute Maximum Ratings
Specified at TA = –40°C to 85°C unless otherwise noted (1)
VCC
Supply voltage
IIK
Input clamping current, VI < 0 V
VSEL
Input control voltages SEL (2) (3)
VI
Input voltage
IOK
Control input clamp current, VO < 0 V
VO
Output voltage
IOL
Current into any output in the low state
IOH
Current into any output in the high state
(1)
(2)
(3)
MIN
MAX
UNIT
–0.5
4.6
V
–50
mA
–0.5
6
V
A port
–0.5
7
B port
–0.5
4.6
A port
–0.5
7
B port
–0.5
4.6
V
–50
A port
40
B port
80
mA
V
mA
–40
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified
VI and VO are used to denote specific conditions for VI/O
6.2 Handling Ratings
Tstg
Storage temperature range
VESD (1)
(1)
(2)
(3)
MIN
MAX
UNIT
–55
150
°C
Human Body Model (HBM), JEDEC: JESD22-A114 (2)
All pins
0
2
IEC61000-4-2 contact discharge (3)
All pins
0
1
kV
Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
(1)
(2)
4
MIN
NOM
MAX
3
3.3
3.6
GTL–
0.85
0.9
0.95
GTL
1.14
1.2
1.26
GTL+
1.35
1.5
1.65
Overall
0.5
2 / 3 VTT
VCC / 2
GTL–
0.5
0.6
0.63
GTL
0.76
0.8
0.84
GTL+
0.87
1
1.1
A port
0
3.3
5.5 (2)
B port
0
VTT
3.6
Supply voltage
A port and DIR
B port
2
VREF + 50 mV
UNIT
V
V
V
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
The VI(max) of LVTTL port is 3.6 V if configured as output (DIR=L)
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VIL
Low-level input voltage
IOH
High-level input current
IOL
Low-level output current
NOM
MAX
A port and DIR
UNIT
0.8
B port
VREF – 50 mV
A port
–20
A port
20
B port
50
V
mA
mA
6.4 Thermal Information
SN74GTL2014
THERMAL METRIC (1)
PW
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
136.8
RθJC(top)
Junction-to-case (top) thermal resistance
63.0
RθJB
Junction-to-board thermal resistance
78.6
ψJT
Junction-to-top characterization parameter
11.9
ψJB
Junction-to-board characterization parameter
77.9
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Specified at TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
VOH
VOL
A port
TEST CONDITIONS
VCC = 3 to 3.6 V, IOH = –100 µA
VCC = 3 V, IOH = –16 mA
–40°C TO 85°C
MIN
TYP
MAX
VCC – 0.2
V
2
A port
VCC = 3 V, IOL = 8 mA
0.28
0.4
A port
VCC = 3 V, IOL = 16 mA
0.55
0.8
B port
VCC = 3 V, IOL = 40 mA
0.23
0.4
A port
II
UNIT
VCC = 3.6 V, VI = VCC
±1
VCC = 3.6, VI = 0 V
±1
VCC = 3.6, VI = 5.5 V
V
µA
5
B port
VCC = 3.6 V, VI = VTT or GND
±1
µA
Control pin
VCC = 3.6 V, VI = VCC or 0 V
±1
µA
OFF-state output current on A port
VCC = 0 V, VIO = 0 to 3.6 V
±10
OFF-state output current on A port
VCC = 0 V, VIO 3.6 to 5.5V
±100
OFF-state output current on B port
VCC = 0 V, VIO = 0 to 3.6 V
±10
A port
VCC = 3.6 V, VI = VCC or GND, IO = 0
3
10
mA
B port
VCC = 3.6 V, VI = VTT or GND, IO = 0
3
10
mA
∆ICC
A port or control input
VCC = 3.6 V, VI = VCC – 0.6 V
500
µA
CI
Input capacitance of control pin
VI = 3.0 V or 0 V
2
2.5
pF
A port
VO = 3 V or 0
4
6
B port
VO = VTT or 0
5.46
5.55
Ioff
ICC
CIO
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6.6 Dynamic Electrical Characteristics
over operating range, TA = –40°C to 85°C, VCC = 1.65 to 4.6 V, GND = 0 V for GTL (see Functional Block Diagram)
PARAMETER
GTL−
GTL
GTL+
VCC = 3.3 V ± 0.3 V
VREF = 0.6 V
VTT = 0.9 V
VCC = 3.3 V ± 0.3 V
VREF = 0.8 V
VTT = 1.2 V
VCC = 3.3 V ± 0.3 V
VREF = 1 V
VTT = 1.5 V
MIN
tPLH (low to high propagation delay)
An to Bn
tPHL(high to low propagation delay)
tPLH (low to high propagation delay)
Bn to An
tPHL (high to low propagation delay)
TYP
MAX
TYP
MAX
2.8
5
MIN
2.8
5
MIN
2.8
5
3.3
7
3.4
7
3.4
7
5.3
8
5.2
8
5.1
8
5.2
8
4.9
7.16
4.7
7.16
UNIT
TYP MAX
ns
ns
6.7 Typical Characteristics
1.2
1.2
VREF
VREF
VTH+
1.1
VTH+
1.1
VTH-
1
1
0.9
0.9
Vth+/Vth-
Vth+/Vth-
VTH-
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.4
0.5
0.6
VREF (V)
0.7
0.8
0.9
1
1.1
1.2
VREF (V)
C001
C002
Figure 1. GTL Vth+ and Vth– vs VREF (25°C)
Figure 2. GTL Vth+ and Vth– vs VREF (–40°C)
1.2
VREF
VTH+
1.1
VTH1
Vth+/Vth-
0.9
0.8
0.7
0.6
0.5
0.4
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VREF (V)
C003
Figure 3. GTL Vth+ and Vth– vs VREF (125°C)
6
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7 Parameter Measurement Information
VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V FOR GTL+
VTT
25 Ω
From Output
Under Test
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR A OUTPUTS
3V
Input
(see Note B)
Test
Point
1.5 V
1.5 V
Input
(see Note B)
VTT
VREF
VREF
0V
0V
tPHL
tPLH
tPHL
tPLH
VOH
VTT
Output
VREF
Output
VREF
1.5 V
1.5 V
VOL
VOL
VOLTAGE WAVEFORM 2
PROPAGATION DELAY TIMES
(B port to A port) †
VOLTAGE WAVEFORM 1
PROPAGATION DELAY TIMES
(A port to B port) †
Input
(see Note B)
VTT
VREF
VREF
Input
(see Note B)
3V
1.5 V
1.5 V
0V
0V
tPHL
tPLH
tPHL
tPLH
VOH
VTT
Output
VREF
Output
VREF
1.5 V
1.5 V
VOL
VOL
VOLTAGE WAVEFORM 3
PROPAGATION DELAY TIMES
(B port to B port)†
VOLTAGE WAVEFORM 4
PROPAGATION DELAY TIMES
(ENn to A port) †
VTT
Input
(see Note B)
VREF
VREF
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPZL
Output
S1 at 2 x VCC
0V
tPZL
tPLZ
VCC
1.5 V
tPLZ
Output
S1 at 2 xVCC
VOL + 0.3 V
VOL
VOLTAGE WAVEFORM 5
PROPAGATION DELAY TIMES
(B port to A (I/O) port) †
VCC
1.5 V
VOL + 0.3 V
VOL
VOLTAGE WAVEFORM 6
ENABLE AND DISABLE TIMES
(EN2 to A (I/O) port) †
† All control inputs are LVTTL levels.
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 4. Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The GTL2014 is a 4-channel translating transceiver designed for 3.3-V LVTTL system interface with a
GTL–/GTL/GTL+ bus, where GTL–/GTL/GTL+ refers to the reference voltage of the GTL bus and the
input/output voltage thresholds associated with it.
The direction pin allows the part to function as either a GTL-to-LVTTL sampling receiver or as a LVTTL-to-GTL
interface.
8.2 Functional Block Diagram
GTL2014
B0
+
–
A0
B1
+
–
A1
B2
+
–
A2
B3
+
–
A3
002aab139
VREF
DIR
8.3 Feature Description
8.3.1 5 V tolerance on LVTTL input
The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V and allows direct access to TTL or 5 V CMOS inputs.
The LVTTL outputs are not 5.5 V tolerant.
8.3.2 3.6 V tolerance on GTL Input/Output
The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage
open-drain output applications.
8.3.3 Ultra-Low VREF and High Bandwidth
GTL2014’s VREF tracks down to 0.5 V for low voltage CPUs with excellent propagation delay performance. This
feature allows the GTL2014 to support high data rates with the GTL– bus.
8.4 Device Functional Modes
The GTL2014 performs translation in two directions. One direction is GTL–/GTL/GTL+ to LVTTL when DIR is tied
to GND. With appropriate VREF set up, the GTL input can be compliant with GTL–/GTL/GTL+. Another direction
is LVTTL to GTL–/GTL/GTL+ when DIR is tied to VCC. 3.6 V tolerance on the GTL output allows the GTL
outputs to pull up to any voltage level under 3.6 V.
8
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
GTL2014 is the voltage translator for GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+. Please find the
reference schematic and recommend value for passive component in the Typical Application.
9.2 Typical Application
9.2.1 GTL–/GTL/GTL+ to LVTTL
Select appropriate VTT/VREF based upon GTL–/GTL/GTL+. The parameters in Recommended Operating
Conditions are compliant to the GTL specification.
3.3 V
GTL
Chipset
1
DIR
2
VCC
14
B0
A0
13
3
B1
A1 12
4
VREF
5
GTL2014PW
GND
11
B2
A2
10
6
B3
A3
9
7
GND
GND
8
LVTTL
FPGA
R
R2
Port_B to Port_A
GTL to LVTTL
R1
VTT
VCC
3.3 V
Vref
2*VTT/3
VTT
1.0 V
DIR
GND
R
75 Ω
R1
49.9 Ω
R2
100 Ω
Figure 5. Application Diagram for GTL to LVTTL
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Typical Application (continued)
9.2.1.1 Design Requirements
The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in Application Information
show standard voltage level and typical resistor values.
NOTE
Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.
9.2.1.2 Detailed Design Procedure
To
1.
2.
3.
begin the design process, determine the following:
Select direction base upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).
Set up appropriate DIR pin and VREF/VTT.
Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to
GTL–/GTL/GTL+).
9.2.1.3 Application Curve
3.30
Input
Output
2.80
Amplitude (V)
2.30
1.80
1.30
0.80
0.30
±0.20
0
1.25
2.5
3.75
5
6.25
7.5
8.75
Time (ns)
C005
Figure 6. GTL-to-LVTTL, VREF = 1 V, VIN = 1.5 V, 100 MHz
10
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Typical Application (continued)
9.2.2 LVTTL/TTL to GTL–/GTL/GTL+
Because GTL is an open-drain interface, the selection of pullup resistor depends on the application requirement
(for example, data rate) and PCB trace capacitance.
3.3 V
GTL
Chipset
1
DIR
2
VCC
14
B0
A0
13
3
B1
A1 12
4
VREF
5
GTL2014PW
GND
11
B2
A2
10
6
B3
A3
9
7
GND
GND
8
LVTTL
FPGA
R
Port_A to Port_B
LVTTL to GTL
VTT
VCC
3.3 V
Vref
GND
VTT
1.0 V
DIR
3.3 V
R
75 Ω
R1
Not Avaliable
R2
Not Avaliable
Figure 7. Application Diagram for LVTTL to GTL
9.2.2.1 Design Requirements
The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in the Application
Information section show standard voltage level and typical resistor values.
NOTE
Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.
9.2.2.2 Detailed Design Procedure
To
1.
2.
3.
begin the design process, determine the following:
Select direction based upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).
Set up appropriate DIR pin and VREF/VTT.
Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to
GTL–/GTL/GTL+).
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Typical Application (continued)
9.2.2.3 Application Curve
2.80E+00
Input (V)
Output (V)
2.30E+00
Amplitude (V)
1.80E+00
1.30E+00
8.00E-01
3.00E-01
-2.00E-01
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
Time (ns)
C001
Figure 8. LVTTL-to-GTL, VREF = 1 V, VTT = 1.5 V, 10 MHz
10 Power Supply Recommendations
Because GTL is a low voltage interface, TI recommends a 0.1-µF decoupling capacitor for VREF.
11 Layout
11.1 Layout Guidelines
Typically, GTL/LVTTL is running at a low data rate; however, the GTL2014 is optimized for excellent propagation
delay, slew rate, bandwidth, and is able support 100-MHz frequencies.
11.2 Layout Example
Short Signal Trace as possible
Minimize Stub as possible
DIR
1
14 VCC
B0
2
13 A0
B1
3
12 A1
VREF
4
B2
5
10 A2
B3
6
9
A3
GND
7
8
GND
GTL2014
11 GND
Figure 9. Layout Example for GTL Trace
12
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: SN74GTL2014
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74GTL2014PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
GT14
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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