SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
FEATURES
•
•
•
•
•
•
•
•
•
•
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
Y Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–12 mA/12 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
•
•
•
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1Y
1T/C
2Y
GND
1OEAB
VCC
1A
GND
2A
2OEAB
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1OEBY
2T/C
2OEBY
GND
1B
ERC
2B
GND
VREF
BIAS VCC
DESCRIPTION/ORDERING INFORMATION
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require
individual output-enable and true/complement controls. The device allows for transparent and inverted
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback
path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating
at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with
the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than
standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing ( VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
5
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
Recommended Operating Conditions (1) (2) (3) (4)
VCC
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
Input clamp current
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
Power-up ramp rate
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
6
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
B port
VTT
Except B port
B port
Except B port
VCC
5.5
V
V
V
VREF + 0.05
V
2
V
B port
VREF – 0.05
Except B port
0.8
V
–18
mA
Y outputs
–12
mA
Y outputs
12
B port
100
Outputs enabled
10
20
–40
mA
ns/V
µs/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable but, generally, GND is connected first.
VTT and RTT can be adjusted to accommodate backplane impedances if the dc-recommended IOL ratings are not exceeded.
VREF can be adjusted to optimize noise margins, but normally it is two-thirds VTT. TI-OPC is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
VIK
VOH
Y outputs
TEST CONDITIONS
VCC = 3.15 V,
II = –18 mA
VCC = 3.15 V to 3.45 V,
IOH = –100 µA
IOH = –6 mA
VCC = 3.15 V
IOH = –12 mA
VCC = 3.15 V
VOL
B port
II (2)
IOZ (2)
ICC
TYP (1) MAX
–1.2
VCC = 3.15 V
2.4
V
0.2
IOL = 6 mA
0.55
IOL = 12 mA
0.8
IOL = 10 mA
0.2
IOL = 64 mA
0.4
IOL = 100 mA
0.55
VCC = 3.45 V,
VI = 0 to 5.5 V
±10
Y outputs
VCC = 3.45 V,
VO = 0 to 5.5 V
±10
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
VO = 0 to 2.3 V
±10
Y outputs or B port
VCC = 3.45 V, IO = 0,
VI (A or control inputs) = VCC or GND,
VI (B port) = VTT or GND
Outputs high
20
Outputs low
20
Outputs disabled
20
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
A-port inputs
Ci
Control inputs
V
2
A-port and
control inputs
∆ICC (3)
UNIT
VCC – 0.2
IOL = 100 µA
VCC = 3.15 V to 3.45 V,
Y outputs
MIN
1.5
VI = 3.15 V or 0
4
4.5
3.5
5
V
µA
µA
mA
mA
pF
Co
Y outputs
VO = 3.15 V or 0
5
5.5
pF
Cio
B port
VO = 1.5 V or 0
7
10.5
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Hot-Insertion Specifications for A Inputs and Y Outputs
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN MAX
UNIT
VCC = 0,
VI or VO = 0 to 5.5 V
10
µA
IOZPU
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
OEBY = 0
±30
µA
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OEBY = 0
±30
µA
Ioff
Live-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
MIN MAX
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
IOZPU
VCC = 0 to 1.5 V,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V,
IOZPD
VCC = 1.5 V to 0,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V,
ICC
(BIAS VCC)
VCC = 0 to 3.15 V
VCC = 3.15 V to 3.45 V
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0 to 1.5 V
VO
VCC = 0,
BIAS VCC = 3.3 V,
IO = 0
IO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0.6 V
UNIT
10
µA
OEAB = 0
±30
µA
OEAB = 0
±30
µA
5
mA
10
µA
0.95
–1
1.05
V
µA
7
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
EDGE RATE (1)
A
B
Slow
A
B
Fast
A
Y
Slow
A
Y
Fast
T/C
B
Slow
T/C
B
Fast
OEAB
B
Slow
OEAB
B
Fast
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
tPHL
tPLH
tPHL
ten
tdis
8
TO
(OUTPUT)
tr
tPLH
(1)
(2)
FROM
(INPUT)
B
Y
T/C
Y
OEBY
Y
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25°C.
MIN TYP (2)
MAX
3.6
6.2
1.7
6
2.7
5.3
1.4
5
4
10.4
3.8
9.8
3.6
9.3
3.4
8.8
3.5
6.6
1.8
6.2
1.4
5.6
2.3
5.5
3.7
6.4
1.5
6.2
2.8
5.3
1.8
5.2
Slow
2.5
Fast
1.3
Slow
3
Fast
2.6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.8
5.6
1.4
5.1
1.7
5.1
1.4
5.1
1
5.1
1
4.8
ns
ns
ns
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
Skew Characteristics
(1)
over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V, standard lumped loads
(CL = 30 pF for B port and CL = 50 pF for Y port) (unless otherwise noted) (see Figure 1)
PARAMETER
tsk(LH)
tsk(LH) (3)
tsk(HL) (3)
tsk(LH) (3)
(3)
tsk(t) (3)
tsk(prLH) (4)
tsk(prHL) (4)
tsk(prLH) (4)
tsk(prHL)
(4)
tsk(prLH) (4)
tsk(prHL) (4)
(1)
(2)
(3)
(4)
TO
(OUTPUT)
EDGE RATE (2)
A
B
Slow
A
B
Fast
B
Y
A
B
B
Y
(3)
tsk(HL) (3)
tsk(HL)
FROM
(INPUT)
MIN
MAX
0.3
0.4
0.3
0.3
0.4
0.2
Slow
1.8
Fast
1.5
UNIT
ns
ns
ns
ns
1
A
B
Slow
A
B
Fast
B
Y
0.7
2
0.5
1.7
1.2
1.6
ns
ns
ns
Actual skew values between GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Slow (ERC = L) and Fast (ERC = H)
tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for
all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any
outputs switching in the same direction, either high to low [tsk(HL)], low to high [tsk(LH)], or in opposite directions, both low to high and high
to low [tsk(t)].
tsk(prLH)/tsk(prHL) – The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices
when both logic devices operate with the same supply voltages and at the same temperature, and have identical package types,
identical specified loads, and identical logic functions. Furthermore, these values are provided by TI SPICE simulations.
9
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
1.5 V
6V
Open
12.5 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
GND
CL = 50 pF
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
S1
Open
6V
GND
Test
Point
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR Y OUTPUTS
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1V
Output
1V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A input to B port)
1V
0V
tPLH
VOH
Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to Y output)
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
1.5 V
tPZL
1.5 V
1V
Input
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
1.5 V
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A input)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
www.ti.com
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
the backplane. See www.ti.com/sc/gtlp for more information.
1.5 V
0.25”
ZO = 50 Ω
1”
Conn.
1”
Conn.
1”
Conn.
Conn.
1”
1”
0.25”
22 Ω
22 Ω
1.5 V
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 19
Slot 20
Drvr
Slot 1
Figure 2. High-Drive Test Backplane
1.5 V
11 Ω
From Output
Under Test
LL = 14 nH
Test
Point
CL = 18 pF
Figure 3. High-Drive RLC Network
11
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
Switching Characteristics
over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
(1)
(2)
12
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE (1)
A
B
Slow
A
B
Fast
A
Y
Slow
A
Y
Fast
tr
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI SPICE models.
TYP (2)
4.3
4.2
3.8
3.4
6.6
6.5
6
6
Slow
1.5
Fast
1
Slow
2.6
Fast
2
UNIT
ns
ns
ns
ns
ns
ns
www.ti.com
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
APPLICATION INFORMATION
Operational Description
The GTLP21395 is designed specifically for use with the TI 1394 backplane layer controller family to transmit the
1394 backplane serial bus across parallel backplanes. But, it is a versatile two 1-bit device that also can provide
multiple 1-bit clocks or an ATM read and write clock in multislot parallel backplane applications.
The 1394-1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a
backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus.
The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100,
200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines the
transmission method, media in the cable version, and protocol. The primary application of the cable version is the
interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal
computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane
version is to provide a robust control interface to each daughter card. The 1394 standard also provides new
services such as real-time I/O and live connect/disconnect capability for external devices.
Electrical
The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both
chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory
space interconnected between devices, or as if devices resided in slots on the main backplane. Device
addressing is 64 bits wide, partitioned as 10 bits for bus ID, 6 bits for node ID, and 48 bits for memory
addresses. The result is the capability to address up to 1023 buses, each having up to 63 nodes and each with
281 terabytes of memory. Memory-based addressing, rather than channel addressing, views resources as
registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a
unit, to be individually addressed, reset, and identified. Multiple nodes can reside physically in a single module,
and multiple ports can reside in a single node.
Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging)
capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as
nodes are added to the bus. A maximum of 63 nodes can be connected to one network.
The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration. Both
environments use dominant mode addresses for arbitration. The backplane environment does not have the
initialization requirements of the cable environment because it is a physical bus and does not contain repeaters.
Due to the differences, a backplane-to-cable bridge is required to connect these two environments.
The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS) encoding.
DS encoding allows only one of the two signal lines to change each data-bit period, essentially doubling the jitter
tolerance with very little additional circuitry overhead in the hardware.
13
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
APPLICATION INFORMATION
Protocol
Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and
transaction layer information to an explicit address. The isochronous format broadcasts data based on channel
numbers, rather than specific addressing. Isochronous packets are issued on the average of each 125 µs in
support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same
interface allows both non-real-time and real-time critical applications on the same bus. The cable environment's
tree topology is resolved during a sequence of events, triggered each time a new node is added or removed from
the network. This sequence starts with a bus reset phase, where previous information about a topology is
cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned, or
it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows each
node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned an
address. After all the information has been gathered on each node, the bus goes into an idle state, waiting for
the beginning of the standard arbitration process.
The backplane physical layer shares some commonality with the cable physical layer. Common functions
include: bus-state determination, bus-access protocols, encoding and decoding functions, and synchronization of
received data to a local clock.
Backplane Features
•
•
•
•
•
25-, 50-, and 100-Mbps data rates for backplane environments
Live connection/disconnection possible without data loss or interruption
Configuration ROM and status registers supporting plug and play
Multidrop or point-to-point topologies supported.
Specified bandwidth assignments for real-time applications
Applicability and Typical Application for IEEE 1394 Backplane
The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP,
FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three
categories:
• Diagnostics
– Alternate control path to the parallel backplane bus
– Test, maintenance, and troubleshooting
– Software debug and support interface
• System enhancement
– Fault tolerance
– Live insertion
– CSR access
– Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus
• Peripheral monitoring
– Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally
wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI)
The 1394 backplane physical layer (PHY) and the SN74GTLP21395 provide a cost-effective way to add
high-speed 1394 connections to every daughter card in almost any backplane. More information on the
backplane PHY devices and how to implement the 1394 standard in backplane and cable applications can be
found at www.ti.com/sc/1394.
14
www.ti.com
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
APPLICATION INFORMATION
SN74GTLP21395 Interface With the TSB14AA1 1394 Backplane PHY
•
•
•
•
•
•
•
•
•
1A, 1B, and 1Y are used for the PHY data signals.
2A, 2B, and 2Y are used for the PHY strobe signals.
PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
1OEBY and 2OEBY are connected to GND because the transceiver always must be able to receive signals
from the backplane and relay them to the PHY.
1T/C and 2T/C are connected to GND for inverted signals.
VCC is nominal 3.3 V.
BIAS VCC is connected to nominal 3.3 V to support live insertion.
VREF normally is 2/3 of VTT.
ERC normally is connected to VCC for slow edge-rate operation because frequencies of only 50 MHz (S100)
and 25 MHz (S50) are required.
Logical Representation
VCC
TSB14AA1
3.3-V VCC
SN74GTLP21395
1 kΩ
TDOE
1OEAB
Tdata 1A
D0-D1
1B
2
BPdata
Rdata 1Y
Host
Interface
CTL0-CTL1
1394
LinkLayer
LREQ
Controller
2
1394
Backplane
PhysicalLayer
Controller
OCDOE
2OEAB
Tstrb 2A
2B
SCLK
BPstrb
Rstrb 2Y
GND
GND
1OEBY
1T/C
GND
2OEBY
2T/C
GND
15
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES350C – JUNE 2001 – REVISED DECEMBER 2005
APPLICATION INFORMATION
Physical Representation
64-Bit Data Bus
32- to 64-Bit Address Bus
GTLP21395 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
STRB
2A
Module
Module
Module
Node
Node
Node
PHY
PHY
PHY
2Y
1A
1Y
VTT
RTT
VTT
2B
STRB
1B
16
DATA
DATA
RTT
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74GTLP21395DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GTLP21395
SN74GTLP21395PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GU395
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74GTLP21395PWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTLP21395PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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