SN74GTLPH1655DGGR

SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • • • • Member of Texas Instruments' Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Partitioned as Two 8-Bit Transceivers With Individual Latch Timing and Output Control, but With a Common Clock LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCES294C – OCTOBER 1999 – REVISED MAY 2005 DGG PACKAGE (TOP VIEW) 1OEAB 1OEBA VCC 1A1 GND 1A2 1A3 GND 1A4 GND 1A5 GND 1A6 1A7 VCC 1A8 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 GND 2A7 VCC 2A8 GND 2OEAB 2OEBA 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CLK 1LEAB 1LEBA ERC GND 1B1 1B2 GND 1B3 1B4 1B5 GND 1B6 1B7 VCC 1B8 2B1 GND 2B2 2B3 GND 2B4 2B5 VREF 2B6 GND 2B7 2B8 BIAS VCC 2LEAB 2LEBA OE DESCRIPTION The SN74GTLPH1655 is a high-drive, 16-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent, latched, and clocked modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (