SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
D
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Member of Texas Instruments’ Widebus
Family
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, or Clock-Enabled Mode
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
LVTTL Interfaces are 5-V Tolerant
Medium-Drive GTLP Outputs (34 mA)
LVTTL Outputs (–32 mA/64 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on A-Port Inputs
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
DGG OR DL PACKAGE
(TOP VIEW)
OEAB
LEAB
A1
GND
A2
A3
VCC (3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC (3.3 V)
A16
A17
GND
A18
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CEAB
CLKAB
B1
GND
B2
B3
VCC (5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
B18
CLKBA
CEBA
The SN74GTLPH16612 is a medium-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of
data transfer. This device provides a high-speed interface between cards operating at LVTTL logic levels and
backplanes operating at GTLP signal levels. High-speed (about two times faster than standard LVTTL or TTL)
backplane operation is a direct result of the reduced output swing ( VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 4 through 7)
VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
IOL
MIN
NOM
MAX
3.3 V
3.15
3.3
3.45
5V
4.75
5
5.25
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port
B port
Except B port
B port
Except B port
High-level output current
Low level output current
Low-level
VREF+50 mV
2
UNIT
V
V
V
V
V
VREF–50 mV
0.8
V
–18
mA
A port
–32
mA
A port
64
B port
34
mA
TA
Operating free-air temperature
–40
85
°C
NOTES: 4. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT, and VREF (any order) last.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
4
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• DALLAS, TEXAS 75265
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
A portt
TEST CONDITIONS
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V,
VCC (3.3 V) = 3.15 V to 3.45 V,
VCC (5 V) = 4.75 V to 5.25 V
3 V) = 3.15
3 15 V,
V
VCC (3
(3.3
VOL
II
A port
IOZL
ICC
(3.3
(3 3 V)
ICC
(5 V)
Ciio
75 V
VCC (5 V) = 4
4.75
IOH = –100 µA
VCC (3.3 V)
–0.2
IOH = –8 mA
IOH = –32 mA
2.4
UNIT
–1.2
V
V
2
IOL = 100 µA
IOL = 16 mA
VCC (5 V) = 4
4.75
75 V
MAX
0.2
0.4
IOL = 32 mA
IOL = 64 mA
0.55
0.5
0.65
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V,
IOL = 34 mA
VCC (3.3 V) = 0 or 3.45 V,
VCC (5 V) = 0 or 5.25 V,
VI = 5.5 V
10
A port
VCC (5 V) = 5.25 V
VI = 5.5 V
VI = VCC (3.3 V)
VI = 0
20
VCC (3.3 V) = 3.45 V,
A port
A port
VCC (3
(3.3
3 V) = 3.45
3 45 V,
V
VCC (5 V) = 5
5.25
25 V
VCC = 0,
VI or VO = 0 to 4.5 V
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
B port
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
A or B
ort
port
VCC (3
(3.3
3 V) = 3
3.45
45 V
V, VCC (5 V) = 5.25
5 25 V,
V IO = 0,
0
VI = VCC (3.3
(3 3 V) or GND§, VI = VTT or GND¶
B port
A port
A or B
ort
port
∆ICC (3.3 V)#
Ci
II = –18 mA
Control
inputs
Ioff
IOZH
VCC (3
(3.3
3 V) = 3.15
3 15 V,
V
TYP†
B port
B port
II(hold)
(
)
MIN
Control
inputs
A port
B port
VCC (3
(3.3
3 V) = 3
3.45
45 V
V, VCC (5 V) = 5.25
5 25 V,
V IO = 0,
0
VI = VCC (3.3
(3 3 V) or GND§, VI = VTT or GND¶
1
5
–5
100
µA
–75
±500
1
VO = 1.5 V
VO = 0
10
–1
VO = 0.65 V
Outputs high
–10
µA
µA
1
Outputs low
5
Outputs disabled
mA
1
Outputs high
120
Outputs low
120
Outputs disabled
120
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, One A-port or control input at 2.7 V,
Other A-port or control inputs at VCC (3.3 V) or GND
1
4
VO = 3.15 V or 0
VO = 1.5 V or 0
µA
75
VI = 0 to VCC (3.3 V)‡
VO = VCC (3.3 V)
VI = 3.15 V or 0
µA
µ
–30
VI = VCC (3.3 V)
VI = 0
VI = 0.8 V
VI = 2 V
V
8.5
8
mA
mA
pF
pF
† All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the VI for A-port or control inputs.
¶ This is the VI for B port.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) (see Figure 1)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
Setup time
Hold time
LEAB or LEBA high
3.3
CLKAB or CLKBA high or low
5.7
A before CLKAB↑
1
B before CLKBA↑
1.8
A before LEAB↓
0.5
B before LEBA↓
1.2
CEAB before CLKAB↑
1.2
CEBA before CLKBA↑
1.4
A after CLKAB↑
1.9
B after CLKBA↑
0.5
A after LEAB↓
2.7
B after LEBA↓
3.5
CEAB after CLKAB↑
1.2
CEBA after CLKBA↑
1.1
MAX
UNIT
85
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
tr
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
FROM
(INPUT)
TO
(OUTPUT)
TYP†
MAX
85
A
B
LEAB
B
CLKAB
B
OEAB
B
6.9
2.5
6.9
3.2
7.3
3.2
7.3
3.4
7.8
3.4
7.8
2.8
7
2.8
7
2.6
Transition time, B outputs (80% to 20%)
B
A
LEBA
A
CLKBA
A
OEBA
A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
2.5
Transition time, B outputs (20% to 80%)
tdis
† All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
6
MIN
ns
ns
ns
ns
ns
2.6
ns
1.5
5.7
1.5
5.7
1.8
5.7
1.8
5.7
2.3
5.5
2.3
5.5
1.8
6.1
1.8
6.1
ns
ns
ns
ns
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
VTT
6V
500 Ω
From Output
Under Test
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
25 Ω
S1
Open
6V
GND
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
tw
3V
Input
3V
Timing
Input
1.5 V
0V
1.5 V
1.5 V
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Input
Test
Point
1.5 V
1.5 V
0V
tPLH
th
3V
Data Input
A Port
1.5 V
Data Input
B Port
VREF
1.5 V
0V
VTT
VREF
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPHL
VTT
Output
VREF
VREF
VOL
3V
Output
Control
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
tPLZ
tPZL
VREF
VREF
1.5 V
0V
VTT
Input
1.5 V
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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7
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The previous switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to an RLC circuit, as shown
in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching
characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better
understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more
information.
38 Ω
.25”
ZO = 70 Ω
2”
2”
.25”
38 Ω
1.5 V
1.5 V
1.5 V
Conn.
Conn.
Conn.
Conn.
19 Ω
1”
1”
1”
Rcvr
1”
Rcvr
From Output
Under Test
Test
Point
Rcvr
CL = 9 pF
Drvr
Slot 1
LL = 19 nH
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
tr
FROM
(INPUT)
TO
(OUTPUT)
TYP†
85
A
B
LEAB
B
CLKAB
B
OEAB
B
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI SPICE models.
8
MIN
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• DALLAS, TEXAS 75265
UNIT
MHz
3.6
3.6
4.3
4.3
4.4
4.4
4.1
4.3
ns
ns
ns
ns
1.4
ns
2.1
ns
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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1
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