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SN74GTLPH306DW

SN74GTLPH306DW

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC24_300MIL

  • 描述:

    IC TXRX LVTTL-GTL 8BIT 24-SOIC

  • 数据手册
  • 价格&库存
SN74GTLPH306DW 数据手册
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on A-Port Data Inputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCES284E – OCTOBER 1999 – REVISED APRIL 2005 DGV, DW, OR PW PACKAGE (TOP VIEW) OE VCC A1 A2 A3 A4 GND A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DIR VREF B1 B2 B3 B4 GND B5 B6 B7 B8 GND DESCRIPTION/ORDERING INFORMATION The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing ( VCC. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Recommended Operating Conditions (1) (2) (3) (4) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate TA Operating free-air temperature (1) (2) (3) (4) 4 MIN NOM MAX UNIT V 3.15 3.3 3.45 GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port Except B port VCC 5.5 VREF + 0.05 VREF – 0.05 Except B port V V V 2 B port V 0.8 V –18 mA A port –24 mA A port 24 B port 50 Outputs enabled 10 ns/V µs/V 20 –40 mA 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL B port A-port and control inputs II (2) MIN TYP (1) MAX TEST CONDITIONS VCC = 3.15 V VCC = 3.15 V –1.2 IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 40 mA 0.4 IOL = 50 mA 0.55 V ±5 VI = 5.5 V B port V V VI = 0 or VCC VCC = 3.45 V UNIT ±20 VI = 0 to 1.5 V µA ±5 IBHL (3) A port VCC = 3.15 V, VI = 0.8 V 75 µA IBHH (4) A port VCC = 3.15 V, VI = 2 V –75 µA IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 µA (6) A port VCC = 3.45 V, VI = 0 to VCC –500 IBHHO ICC A or B port ∆ICC Ci Cio (1) (2) (3) (4) (5) (6) (7) VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND µA Outputs high 20 Outputs low 20 Outputs disabled 20 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND (7) mA 1.5 mA pF Control inputs VI = 3.15 V or 0 4.5 5 A port VO = 3.15 V or 0 7.5 9 B port VO = 1.5 V or 0 7.5 9 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter II includes the off-state output leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA MAX UNIT Hot-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 1.5 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 1.5 V, MIN 10 µA OE = 0 ±30 µA OE = 0 ±30 µA 5 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL ten tdis tr A B OE B MIN TYP (1) MAX 1 7.5 1 7.5 1 8 1 8 UNIT ns ns Rise time, B outputs (20% to 80%) 2.2 ns tf Fall time, B outputs (80% to 20%) 2.1 ns Rise time, A outputs (10% to 90%) 4.1 ns tf Fall time, A outputs (90% to 10%) 3.3 ns tPHL ten tdis 6 TO (OUTPUT) tr tPLH (1) FROM (INPUT) B A OE A All typical values are at VCC = 3.3 V, TA = 25°C. 1 7 1 7 1 8 1 8 ns ns SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 7 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 1.5 V 1.5 V 0.25” ZO = 70 Ω 2” Conn. Conn. 1” 1” Conn. 1” 2” 0.25” 38 Ω 38 Ω 1.5 V 19 Ω From Output Under Test Conn. LL = 19 nH 1” Test Point CL = 9 pF Rcvr Rcvr Rcvr Slot 2 Slot 9 Slot 10 Drvr Slot 1 Figure 3. Medium-Drive RLC Network Figure 2. Medium-Drive Test Backplane Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL ten tdis (1) 8 FROM (INPUT) TO (OUTPUT) A B OE B TYP (1) 3.6 4.1 4.4 4.6 UNIT ns ns tr Rise time, B outputs (20% to 80%) 1.2 ns tf Fall time, B outputs (80% to 20%) 2.2 ns All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74GTLPH306DGVR ACTIVE TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GH306 Samples SN74GTLPH306DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GTLPH306 Samples SN74GTLPH306DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GTLPH306 Samples SN74GTLPH306PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GH306 Samples SN74GTLPH306PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GH306 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN74GTLPH306DW 价格&库存

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