SN74HC00, SN54HC00
SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
SNx4HC00 Quadruple 2-Input NAND Gates
1 Features
3 Description
•
•
•
This device contains four independent 2-input NAND
Gates. Each gate performs the Boolean function
Y = A ● B in positive logic.
•
•
Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range:
–40°C to +85°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
SN74HC00D
SOIC (14)
8.70 mm × 3.90 mm
2 Applications
SN74HC00DB
SSOP (14)
6.50 mm × 5.30 mm
•
•
SN74HC00N
PDIP (14)
19.30 mm × 6.40 mm
SN74HC00NS
SO (14)
10.20 mm × 5.30 mm
SN74HC00PW
TSSOP (14)
5.00 mm × 4.40 mm
SN54HC00FK
LCCC (20)
8.90 mm × 8.90 mm
SN54HC00J
CDIP (14)
21.30 mm × 7.60 mm
SN54HC00W
CFP (14)
9.20 mm × 6.29 mm
Alarm / tamper detect circuit
S-R latch
(1)
1A
1B
1Y
2A
2B
2Y
GND
For all available packages, see the orderable addendum at
the end of the data sheet.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
Device Functional Pinout
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HC00, SN54HC00
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SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics - Commercial (74xx) .......... 5
6.6 Electrical Characteristics - Military (54xx) .................. 6
6.7 Switching Characteristics - Commercial (74xx) ......... 6
6.8 Switching Characteristics - Military (54xx) ................. 6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Balanced CMOS Push-Pull Outputs........................... 9
8.4 Standard CMOS Inputs...............................................9
8.5 Clamp Diode Structure................................................9
8.6 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................14
11 Layout........................................................................... 14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.4 Trademarks............................................................. 15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2021) to Revision H (August 2021)
Page
• Increased D and PW package thermal values...................................................................................................5
Changes from Revision F (July 2016) to Revision G (January 2021)
Page
• Updated to new data sheet format......................................................................................................................1
• Updated D and PW package thermals to new standards................................................................................... 5
Changes from Revision E (August 2003) to Revision F (July 2016)
Page
• Added Applications section, Device Information table, ESD Ratings table, Typical Characteristics section,
Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.............................................................................. 1
• Added Military Disclaimer to Features list...........................................................................................................1
• Removed Ordering Information table; see POA at the end of data sheet.......................................................... 1
• Changed values in the Thermal Information table to align with JEDEC standards............................................ 5
• Deleted Operating Characteristics table; moved Cpd row to Electrical Characteristics .................................... 5
2
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5 Pin Configuration and Functions
1B 1A NC VCC 4B
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
1Y
4
3
2
1
20 19
18
4A
NC
5
17
NC
4Y
2A
4
11
4Y
2B
5
10
3B
2A
6
16
2Y
6
9
3A
NC
7
15
NC
GND
7
8
3Y
2B
8
14
9 10 11 12 13
3B
D, DB, N, NS, PW, J, or W Package
14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP
Top View
2Y GND NC 3Y 3A
FK Package
20-Pin LCCC
Top View
Table 5-1. Pin Functions
PIN
D, DB, N,
NS, PW, J,
or W
FK
1A
1
2
Input
Channel 1, Input A
1B
2
3
Input
Channel 1, Input B
1Y
3
4
Output
2A
4
6
Input
Channel 2, Input A
2B
5
8
Input
Channel 2, Input B
2Y
6
9
Output
3A
9
13
Input
Channel 3, Input A
3B
10
14
Input
Channel 3, Input B
3Y
8
12
Output
4A
12
18
Input
Channel 4, Input A
4B
13
19
Input
Channel 4, Input B
4Y
11
16
Output
GND
7
NAME
NC
VCC
14
I/O
DESCRIPTION
Channel 1, Output Y
Channel 2, Output Y
Channel 3, Output Y
Channel 4, Output Y
10
—
Ground
1, 5, 7, 11, 15,
17
—
Not internally connected
20
—
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC +
0.5 V
IOK
Output clamp current(2)
VO < –0.5 V or VO > VCC +
0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±20
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature(3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
3.15
0.5
VCC = 4.5 V
1.35
TA
4
Operating free-air temperature
0
VCC
V
VCC
V
1000
VCC = 4.5 V
500
VCC = 6 V
400
SN54HC00
–55
125
SN74HC00
–40
85
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V
1.8
0
VCC = 2 V
Input transition rise and fall time
V
4.2
VCC = 6 V
tt
V
1.5
VCC = 2 V
VIL
UNIT
ns
°C
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6.4 Thermal Information
SN74HC00
THERMAL
METRIC(1)
UNIT
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SOP)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
Junction-to-ambient thermal
resistance
133.6
108.3
57.5
91.0
151.7
°C/W
Junction-to-case (top) thermal
resistance
89.0
60.3
45.1
48.8
79.4
°C/W
RθJB
Junction-to-board thermal
resistance
89.5
55.7
37.3
49.8
94.7
°C/W
ΨJT
Junction-to-top characterization
parameter
45.5
25
30.3
18.4
25.2
°C/W
ΨJB
Junction-to-board
characterization parameter
89.1
55.2
37.2
49.5
94.1
°C/W
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
RθJA
Rθ
JC(top)
Rθ
JC(bot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics - Commercial (74xx)
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER
VOH
VOL
High-level
output voltage
TEST CONDITIONS
VI = VIH
or VIL
Low-level output VI = VIH
voltage
or VIL
IOH = -20 µA
VCC
25°C
-40°C to 85°C
MIN
TYP
2V
1.9
1.998
1.9
4.5 V
4.4
4.499
4.4
6V
5.9
5.999
5.9
MIN
IOH = -4 mA
4.5 V
3.98
4.3
3.84
IOH = -5.2 mA
6V
5.48
5.8
5.34
IOL = 20 µA
TYP
MAX
V
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
6V
V
0.001
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.33
IOL = 5.2 mA
6V
0.15
0.26
0.33
±0.1
±100
±1000
µA
2
20
µA
10
10
pF
II
Input leakage
current
VI = VCC or 0
6V
ICC
Supply current
VI = VCC
or 0
6V
Ci
Input
capacitance
2 V to 6 V
3
Cpd
Power
dissipation
No load
capacitance per
gate
2 V to 6 V
20
(1)
(2)
MAX
UNIT
VI = VCC or 0
pF
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
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6.6 Electrical Characteristics - Military (54xx)
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER
VOH
VOL
High-level
output voltage
TEST CONDITIONS
VI = VIH
or VIL
Low-level output VI = VIH
voltage
or VIL
VCC
IOH = -20 µA
25°C
MIN
TYP
2V
1.9
1.998
1.9
4.5 V
4.4
4.499
4.4
6V
5.9
5.999
5.9
MIN
4.5 V
3.98
4.3
3.7
IOH = -5.2 mA
6V
5.48
5.8
5.2
TYP
MAX
V
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
6V
0.001
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.4
IOL = 5.2 mA
6V
0.15
0.26
0.4
±0.1
±100
±1000
nA
2
40
µA
10
10
pF
II
Input leakage
current
VI = VCC or 0
6V
ICC
Supply current
VI = VCC
or 0
6V
Ci
Input
capacitance
2 V to 6 V
3
Cpd
Power
dissipation
No load
capacitance per
gate
2 V to 6 V
20
(1)
(2)
MAX
IOH = -4 mA
IOL = 20 µA
UNIT
-55°C to 125°C
VI = VCC or 0
V
pF
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
6.7 Switching Characteristics - Commercial (74xx)
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
tt
Propagation delay
A or B
Transition-time
Y
Y
MIN
TYP
UNIT
TYP
MAX
45
90
115
4.5 V
9
18
23
6V
8
15
20
2V
2V
tpd
–40°C to 85°C
MAX
38
75
95
4.5 V
8
15
19
6V
6
13
16
ns
ns
6.8 Switching Characteristics - Military (54xx)
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
6
Propagation delay
A or B
Y
MAX
45
90
135
4.5 V
9
18
27
6V
8
15
23
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MIN
TYP
UNIT
TYP
2V
tpd
–55°C to 125°C
MAX
ns
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over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
TYP
MAX
38
75
110
4.5 V
8
15
22
6V
6
13
19
2V
tt
Transition-time
Y
UNIT
–55°C to 125°C
MIN
TYP
MAX
ns
6.9 Typical Characteristics
TA = 25°C
0.3
7
VOL Output Low Voltage (V)
VOH Output High Voltage (V)
6
5
4
3
2
2-V
4.5-V
6-V
1
0
2-V
4.5-V
6-V
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
IOH Output High Current (mA)
5
6
Figure 6-1. Typical Output Voltage in the High State (VOH)
0
1
2
3
4
IOL Output Low Current (mA)
5
6
Figure 6-2. Typical Output Voltage in the Low State (VOL)
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
VCC
Input
50%
50%
0V
From Output
Under Test
tPHL(1)
tPLH(1)
VOH
CL(1)
Output
50%
50%
VOL
(1) CL includes probe and test-fixture capacitance.
tPLH(1)
tPHL(1)
Figure 7-1. Load Circuit for Push-Pull Outputs
VOH
Output
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times
8
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B
in positive logic.
8.2 Functional Block Diagram
xA
xY
xB
8.3 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.4 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated
at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.5 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
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VCC
Device
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.6 Device Functional Modes
Table 8-1. Function Table
INPUTS
10
OUTPUT
A
B
Y
H
H
L
L
X
H
X
L
H
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HC00 is used to create an active-low SR latch. The two additional gates can be
used for a second active-low SR latch, individually used for their logic function, or the inputs can be grounded
and both channels left unused. This device is used to drive the tamper indicator LED and provide one bit of
data to the system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output
remains HIGH until the system controller addresses the event and sends a LOW signal to the R input which
returns the Q output back to LOW.
9.2 Typical Application
System
Controller
R1
R
Tamper
Switch
Q
S
R2
Tamper
Indicato r
Figure 9-1. Typical Application Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HC00 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HC00 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The SN74HC00 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50
pF.
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The SN74HC00 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC00, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The SN74HC00 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
12
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SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC00
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
R
S
Q
Figure 9-2. Application Timing Diagram
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SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
1OE
1
VCC
GND
0.1 F
Bypass capacitor
placed close to the
device
1A1
2
20
19
2Y4
3
18
1Y1
Unused input
tied to GND 1A2
4
17
2A4
2Y3
5
16
1Y2 Unused output
1A3
6
15
2A3
1Y3
Avoid 90°
corners for
signal lines
GND
2OE
left floating
2Y2
7
14
1A4
8
13
2A2
2Y1
9
10
12
11
1Y4
GND
2A1
Figure 11-1. Example layout for the SN74HC00 in the RKS Package
14
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SN74HC00, SN54HC00
www.ti.com
SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74HC00 SN54HC00
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8403701VCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8403701VC
A
SNV54HC00J
5962-8403701VDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8403701VD
A
SNV54HC00W
84037012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84037012A
SNJ54HC
00FK
8403701CA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8403701CA
SNJ54HC00J
Samples
8403701DA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8403701DA
SNJ54HC00W
Samples
JM38510/65001B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001B2A
Samples
JM38510/65001BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001BCA
Samples
JM38510/65001BDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001BDA
Samples
M38510/65001B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001B2A
Samples
M38510/65001BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001BCA
Samples
M38510/65001BDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65001BDA
Samples
SN54HC00J
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC00J
Samples
SN74HC00D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HC00DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DTE4
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00DTG4
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU | SN
N / A for Pkg Type
-40 to 85
SN74HC00N
Samples
SN74HC00NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC00N
Samples
SN74HC00NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SN74HC00PWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC00
Samples
SNJ54HC00FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84037012A
SNJ54HC
00FK
SNJ54HC00J
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8403701CA
SNJ54HC00J
Samples
SNJ54HC00W
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8403701DA
SNJ54HC00W
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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