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SN74HC05DR

SN74HC05DR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC14_150MIL

  • 描述:

    带开路漏极输出的六角逆变器

  • 数据手册
  • 价格&库存
SN74HC05DR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 SNx4HC05 Hex Inverters With Open-Drain Outputs 1 Features 3 Description • • • • • • The SNx4HC05 devices contain six independent inverters. They perform the Boolean function Y = A in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. 1 Wide Operating Voltage Range of 2 V to 6 V Outputs can Drive up to 10 LSTTL Loads Low-Power Consumption, 20-μA Maximum ICC Typical tpd = 8 ns ±4-mA Output Drive at 5 V Low Input Current of 1-μA Maximum Device Information(1) 2 Applications • • • • • • PART NUMBER Mice Printers AC Inverter Drives UPS AC Servo Drives Other Motor Drives space space space SN74HC05 PACKAGE BODY SIZE (NOM) PDIP (14) 19.30 mm × 6.40 mm SOIC (14) 8.65 mm × 3.91 mm SOP (14) 10.30 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) A Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 6 Detailed Description .............................................. 7 8.1 Overview ................................................................... 7 8.2 Functional Block Diagram ......................................... 7 8.3 Feature Description................................................... 7 8.4 Device Functional Modes.......................................... 7 9 Application and Implementation .......................... 8 9.1 Application Information.............................................. 8 9.2 Typical Application ................................................... 8 10 Power Supply Recommendations ....................... 9 11 Layout..................................................................... 9 11.1 Layout Guidelines ................................................... 9 11.2 Layout Example ...................................................... 9 12 Device and Documentation Support ................. 10 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 10 13 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History Changes from Revision D (August 2003) to Revision E • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 SN54HC05, SN74HC05 www.ti.com SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 5 Pin Configuration and Functions SN74HC05: D, N, NS, or PW Package, 14-Pin SOIC, PDIP, SOP, or TSSOP SN54HC05: J or W Package, 19-Pin CDIP or CFP (Top View) 14 2 13 3 12 4 11 5 10 6 9 7 8 1Y 1A NC VCC 6A 1 VCC 6A 6Y 5A 5Y 4A 4Y 2A NC 2Y NC 3A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A 1A 1Y 2A 2Y 3A 3Y GND SN54HC05: FK Package 20-Pin LCCC (Top View) NC – No internal connection Pin Functions PIN NAME I/O DESCRIPTION NO. LCCC NO. 1A 1 2 I Input 1 1Y 2 3 O Output 1 2A 3 4 I Input 2 2Y 4 6 O Output 2 3A 5 8 I Input 3 3Y 6 9 O Output 3 GND 7 10 – Ground pin 4A 9 13 I Input 4 4Y 8 12 O Output 4 5A 11 16 I Input 5 5Y 10 14 O Output 5 6A 13 19 I Input 6 6Y 12 18 O Output 6 NC – 1, 5, 7, 11, 15, 17 – No connect VCC 14 20 – Power pin Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 3 SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VCC (1) Supply voltage (2) MIN MAX UNIT –0.5 7 V IIK Input clamp current, VI < 0 or VI > VCC –20 20 mA IOK Output clamp current, VO < 0 or VO > VCC (2) –20 20 mA IO Continuous output current, VO = 0 to VCC –25 25 mA Continuous current through VCC or GND –50 50 mA Storage temperature –65 150 °C Tstg (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See (1) VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 Low-level input voltage V 1.5 3.15 V 4.2 VCC = 2 V VIL UNIT 0.5 VCC = 4.5 V 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V Δt/Δv TA (1) 4 Input transition rise or fall time Operating free-air temperature 1000 VCC = 4.5 V 500 VCC = 6 V 400 SN54HC05 –55 125 SN74HC05 –40 125 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 SN54HC05, SN74HC05 www.ti.com SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 6.4 Thermal Information SN74HC05 THERMAL METRIC (1) D (SOIC) N (PDIP) NS (SOP) PW (TSSOP) 14 PINS 14 PINS 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 89.1 85.9 86.4 117.1 RθJC(top) Junction-to-case (top) thermal resistance 50.6 43.8 42.4 46.1 RθJB Junction-to-board thermal resistance 43.3 44.6 45.1 58.7 ψJT Junction-to-top characterization parameter 16.3 12 11.8 4.8 ψJB Junction-to-board characterization parameter 43 44.2 44.7 58.1 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C VCC MIN IOH IOL = 20 µA MIN 0.01 0.5 10 5 5 2V 0.002 0.1 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 0.33 6V 0.15 0.26 0.4 0.33 0.33 ±0.1 ±100 ±1000 ±1000 ±1000 nA 2 40 20 20 µA 10 10 10 10 pF II VI = VCC or 0 6V ICC VI = VCC or 0, IO = 0 6V 2 to 6 V 3 MAX MAX MIN UNIT 6V IOL = 5.2 mA Ci MIN SN74HC05 –40°C to 125°C MAX VI = VIH or VIL IOL = 4 mA SN74HC05 –40°C to 85°C TYP VI = VIH or VIL, VO = VCC VOL SN54HC05 MAX µA V 6.6 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tf FROM (INPUT) TO (OUTPUT) VCC A Y A Y Y TA = 25°C MIN SN74HC05 –40°C to 85°C SN54HC05 MIN MAX MIN SN74HC05 –40°C to 125°C TYP MAX MAX MIN 2V 60 115 175 145 160 4.5 V 13 23 35 29 31 6V 10 20 30 25 28 2V 45 85 130 105 120 4.5 V 9 17 26 21 23 6V 8 14 22 18 21 2V 38 75 110 95 110 4.5 V 8 15 22 19 22 6V 6 13 19 16 19 UNIT MAX ns 6.7 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per inverter No load TYP 20 UNIT pF Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 5 SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 www.ti.com 6.8 Typical Characteristics 14.5 70 14 60 50 TPD (ns) TPD (ns) 13.5 13 12.5 40 30 20 12 10 0 11.5 -100 -50 0 50 Temperature 100 0 150 2 4 VCC D001 Figure 1. TPD vs. Temperature at 4.5 V, 25°C 6 8 D002 Figure 2. TPD vs. VCC at 25°C 7 Parameter Measurement Information VCC RL = 1 kΩ From Output Under Test VCC Test Point Input tPLH In-Phase Output LOAD CIRCUIT Input 50% 10% 50% 10% 0 V tr tPHL 90% 10% tPHL VCC 90% 50% 0V CL = 50 pF (see Note A) 90% 50% Out-of-Phase Output 90% tPLH 50% 10% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 50% 10% V OL tf 10% VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 3. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 SN54HC05, SN74HC05 www.ti.com SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 8 Detailed Description 8.1 Overview The SNx4HC05 devices contain six independent inverters. They perform the Boolean function Y = A in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other opendrain outputs to implement active-low wired-OR or active-high wired-AND functions. 8.2 Functional Block Diagram A Y Figure 4. Logic Diagram (Positive Logic) 8.3 Feature Description The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The strong current-sinking outputs allow the device to drive medium loads without significant increases in output voltage. In addition, the low power consumption makes this device a good choice for portable and battery powersensitive applications. 8.4 Device Functional Modes Table 1. Function Table (Each Inverter) INPUT A OUTPUT Y H L L H Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 7 SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74HC05 device is a low drive open-drain CMOS device that can be used for a multitude of buffer type functions. The open-drain output can be pulled to any voltage between GND and VCC making them Ideal for down translation. 9.2 Typical Application Buffer Function Basic LED Driver VPU Wired OR uC or Logic uC or Logic HC05 VPU uC or Logic HC05 uC or Logic HC05 Figure 5. Simplified Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and is open-drain so it has low-output drive only. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. Parallel output drive can create fast edges into light loads so consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure • Recommended input conditions: – Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions. – Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions. • Recommended output conditions: – Load currents should not exceed 25 mA per output and 50 mA total for the part. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 SN54HC05, SN74HC05 www.ti.com SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 Typical Application (continued) 9.2.3 Application Curve 2 VIL (V) 1.5 1 0.5 0 0 1 2 3 4 VCC (V) 5 6 7 D001 Figure 6. Max VIL vs. VCC Level 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC terminals, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. 11.2 Layout Example Figure 7. Layout Recommendation Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 9 SN54HC05, SN74HC05 SCLS080E – FEBRUARY 2015 – REVISED MARCH 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs, SCBA004 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54HC05 Click here Click here Click here Click here Click here SN74HC05 Click here Click here Click here Click here Click here 12.3 Trademarks All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN54HC05 SN74HC05 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-88718012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596288718012A SNJ54HC 05FK 5962-8871801CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8871801CA SNJ54HC05J SN54HC05J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC05J SN74HC05D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05DTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 125 SN74HC05N SN74HC05NE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 125 SN74HC05N SN74HC05NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 SN74HC05PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC05 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SNJ54HC05FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596288718012A SNJ54HC 05FK SNJ54HC05J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8871801CA SNJ54HC05J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN74HC05DR 价格&库存

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SN74HC05DR
  •  国内价格
  • 1+0.90166
  • 100+0.84155
  • 300+0.78144
  • 500+0.72132
  • 2000+0.69127
  • 5000+0.67324

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