SN74HC109N

SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features 2 Description • • • • • • These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flipflops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. Wide operating voltage range of 2 V to 6 V Low input current of 1 μA max High-current outputs drive up to 10 LSTTL loads Low power consumption, 40-μA max ICC Typical tpd = 12 ns ±4-mA output drive at 5 V Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN54HC109J CDIP (16) 24.38 mm × 6.92 mm SN74HC109D SOIC (16) 9.90 mm × 3.90 mm SN74HC109N PDIP (16) 19.31 mm × 6.35 mm SN74HC109NS SO (16) 6.20 mm × 5.30 mm SNJ54HC109FK LCCC (20) 8.89 mm × 8.45 mm SNJ54HC109W CFP (16) 10.16 mm × 6.73 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions(1) .................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Timing Requirements.................................................. 5 5.6 Switching Characteristics ...........................................6 5.7 Operating Characteristics........................................... 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2022) to Revision C (June 2022) Page • Junction-to-ambient thermal resistance values increased. D was 73 is now 117.2, N was 67 is now 60.5, NS was 64 is now 88.3............................................................................................................................................. 4 Changes from Revision A (October 2003) to Revision B (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 4 Pin Configuration and Functions J, W, D, N, or NS Package 16-Pin CDIP, CFP, SOIC, PDIP, or SO Top View NC - No internal connection FK Package 20-Pin LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 3 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 7 UNIT VCC Supply voltage range IIK Input clamp current VI < 0 or VI > VCC ±20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA 300 ℃ 260 ℃ 150 ℃ 150 ℃ Continuous current through VCC or GND V FK package Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J package W package D package Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds N package NS package TJ Junction temperature Tstg Storage temperature range (1) –65 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions(1) SN54HC109 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VIL Low-level input voltage SN74HC109 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 UNIT V V 4.2 VCC = 2 V 0.3 0.5 VCC = 4.5 V 0.9 1.35 VCC = 6 V 1.2 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv Input transition rise/fall time TA Operating free-air temperature VCC = 2 V VCC = 4.5 V VCC = 6 V (1) 1000 1000 500 500 400 −55 125 ns 400 −40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5.3 Thermal Information THERMAL METRIC 4 (1) D (SOIC) N (PDIP) NS (SO) 16 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 117.2 60.5 88.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.2 47.9 45.9 °C/W RθJB Junction-to-board thermal resistance 75.6 40.4 50.9 °C/W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 5.3 Thermal Information (continued) THERMAL METRIC D (SOIC) N (PDIP) NS (SO) 16 PINS 16 PINS 16 PINS UNIT ψJT Junction-to-top characterization parameter 38.1 27.3 12.9 °C/W ψJB Junction-to-board characterization parameter 75.3 40.2 50.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC MIN 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 IOL = 4 mA 5.2 UNIT V 5.34 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 4 80 40 μA 10 10 10 pF IO = 0 Ci 5.8 MAX 2V IOL = 5.2 mA VI = VCC or 0, SN74HC109 MAX 1.9 IOL = 20 μA VI = VCC or 0 MIN 2V VI = VIH or VIL II SN54HC109 MAX 4.5 V VI = VIH or VIL ICC TYP IOH = −20 μA IOH = −5.2 mA VOL TA = 25°C MIN 6V 2 V to 6 V 3 V 5.5 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency TA = 25°C MIN tw Pulse duration CLK high or low MIN SN74HC109 MAX MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V PRE or CLR low SN54HC109 MAX 36 25 UNIT MHz 29 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 5 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 over recommended operating free-air temperature range (unless otherwise noted) VCC Data (J, K) tsu Setup time before CLK ↑ PRE or CLR inactive th Hold time Data after CLK↑ TA = 25°C MIN SN54HC109 MAX MIN SN74HC109 MAX MIN 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 25 40 30 4.5 V 5 8 6 6V 4 7 5 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 MAX UNIT ns ns 5.6 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK Q or Q tt Q or Q VCC TA = 25°C SN54HC109 MAX MIN SN74HC109 MIN TYP MAX MIN 2V 6 10 4.2 5 4.5 V 31 50 21 25 6V 36 60 25 29 MAX UNIT ns 2V 60 230 345 290 4.5 V 15 46 69 58 6V 12 39 59 49 2V 50 175 250 220 4.5 V 15 35 50 44 6V 12 30 42 37 2V 28 75 110 95 4.5V 8 15 22 19 6V 6 13 19 16 ns ns 5.7 Operating Characteristics TA = 25℃ PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance per buffer/driver No load Submit Document Feedback TYP UNIT 35 pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 6 Parameter Measurement Information A. B. C. D. E. F. G. CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. The outputs are measured one at a time with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. Figure 6-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 7 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 7 Detailed Description 7.1 Overview These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Function Table INPUTS (1) 8 OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H(1) H(1) H H ↑ L L L H H H ↑ H L H H ↑ L H H H ↑ H H H L H H L X X Q0 Q0 Toggle Q0 Q0 This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 9 SN54HC109, SN74HC109 www.ti.com SCLS470C – MARCH 2003 – REVISED JUNE 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC109 SN74HC109 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8415001VFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8415001VF A SNV54HC109W 84150012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84150012A SNJ54HC 109FK 8415001EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8415001EA SNJ54HC109J Samples 8415001FA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8415001FA SNJ54HC109W Samples JM38510/65304BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65304BEA Samples M38510/65304BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65304BEA Samples SN54HC109J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC109J Samples SN74HC109D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 Samples SN74HC109DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC109 Samples SN74HC109DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 Samples SN74HC109N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC109N Samples SN74HC109NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC109N Samples SN74HC109NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 Samples SNJ54HC109FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84150012A SNJ54HC 109FK SNJ54HC109J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8415001EA SNJ54HC109J Samples SNJ54HC109W ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8415001FA SNJ54HC109W Samples Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of