SN54HC138, SN74HC138
SCLS107G – DECEMBER 1982 – REVISED OCTOBER 2021
SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers
1 Features
3 Description
•
The SNx4HC138 devices are designed to be used
in high-performance memory-decoding or data-routing
applications requiring very short propagation delay
times. In high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When employed with high-speed
memories using a fast enable circuit, the delay times
of these decoders and the enable time of the memory
are usually less than the typical access time of the
memory. This means that the effective system delay
introduced by the decoders is negligible.
•
•
•
•
•
•
•
•
Targeted Specifically for High-Speed Memory
Decoders and Data-Transmission Systems
Wide Operating Voltage Range (2 V to 6 V)
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
Active Low Outputs ( Selected Output is Low)
Incorporate Three Enable Inputs to Simplify
Cascading or Data Reception
2 Applications
•
•
•
•
•
•
LED Displays
Servers
White Goods
Power Infrastructure
Building Automation
Factory Automation
Device Information
PART NUMBER
PACKAGE
(1)
BODY SIZE (NOM)
SN74HC138D
SOIC (16)
9.90 mm x 3.90 mm
SN74HC138DB
SSOP (16)
6.20 mm x 5.30 mm
SN74HC138N
PDIP (16)
19.32 mm x 6.35 mm
SN74HC138NS
SO (16)
10.20 mm x 5.30 mm
SN74HC138PW
TSSOP (16)
5.00 mm x 4.40 mm
SN54HC138J
CDIP (16)
21.34 mm x 6.92 mm
SN54HC138W
CFP (16)
10.16 mm x 6.73 mm
SN54HC138FK
LCCC (20)
8.89 mm x 8.89 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Functional Block DIagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings: SN74HC138......................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information: SN74HC138..............................5
6.5 Thermal Information: SN54HC138..............................5
6.6 Electrical Characteristics.............................................5
6.7 Electrical Characteristics: SN74HC138...................... 6
6.8 Electrical Characteristics: SN54HC138...................... 6
6.9 Switching Characteristics............................................6
6.10 Switching Characteristics: SN74HC138....................7
6.11 Switching Characteristics: SN54HC138....................7
6.12 Typical Characteristic................................................7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Documentation Support.......................................... 13
12.2 Related Links.......................................................... 13
12.3 Receiving Notification of Documentation Updates..13
12.4 Support Resources................................................. 13
12.5 Trademarks............................................................. 13
12.6 Electrostatic Discharge Caution..............................13
12.7 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2003) to Revision F (September 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Changed RθJA values from 73 to 87.3 (D), from 82 to 104.3 (DB), from 67 to 54.8 (N), from 64 to 91.1 (NS),
and from 108 to 114.6 (PW)................................................................................................................................5
Changes from Revision F (September 2016) to Revision G (October 2021)
Page
• Updated the ESD ratings table to fit modern data sheet standards....................................................................4
2
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5 Pin Configuration and Functions
SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP
Package
16-Pin D, DB, N, NS, PW, J or W
Top View
NC: No internal connection
LCCC Package
20-Pin FK
Top View
Pin Functions
PIN
I/O(1)
DESCRIPTION
SOIC, SSOP, PDIP, SO,
TSSOP, CDIP, CFP
LCCC
A
1
2
I
Select input A (least significant bit)
B
2
3
I
Select input B
C
3
4
I
Select input C (most significant bit)
G2A
4
5
I
Active low enable A
G2B
5
7
I
Active low enable B
G1
6
8
I
Active high enable
GND
8
10
—
Ground
NC
—
1, 6, 11, 16
—
No internal connection
VCC
16
20
—
Supply voltage
Y0
15
19
O
Output 0 (least significant bit)
Y1
14
18
O
Output 1
Y2
13
17
O
Output 2
Y3
12
15
O
Output 3
Y4
11
14
O
Output 4
Y5
10
13
O
Output 5
Y6
9
12
O
Output 6
Y7
7
9
O
Output 7 (most significant bit)
NAME
(1)
Signal Types: I = Input, O = Output, I/O = Input or Output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
MIN
MAX
UNIT
–0.5
7
V
VI < 0 or VI > VCC
±20
mA
VO < 0 or VO > VCC
±20
mA
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Supply voltage range
(2)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
(2)
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings: SN74HC138
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
V
4.2
0.5
VCC = 4.5 V
Low-level input voltage
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
Δt/Δv
Cpd
TA
(1)
4
V
1.5
3.15
VCC = 2 V
VIL
UNIT
Input transition rise or fall time
1000
VCC = 4.5 V
500
VCC= 6 V
400
Power dissipation capacitance (no load)
Operating free-air temperature
85
ns
pF
SN54HC138
–55
125
SN74HC138
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See TI application report, Implications
of Slow or Floating CMOS Inputs (SCBA004).
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6.4 Thermal Information: SN74HC138
SN74HC138
THERMAL
METRIC(1)
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
87.3
104.3
54.8
91.1
141.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.8
54.7
42.1
49.5
49.5
°C/W
RθJB
Junction-to-board thermal resistance
44.8
54.9
34.8
51.5
59.6
°C/W
ψJT
Junction-to-top characterization parameter
14.2
17.7
27
17.8
6.9
°C/W
ψJB
Junction-to-board characterization
parameter
44.5
54.4
34.7
51.2
59.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: SN54HC138
SN54HC138(2)
THERMAL METRIC(1)
J (CDIP)
W (CFP)
FK (LCCC)
16 PINS
16 PINS
20 PINS
—
—
—
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
17.7
(1)
UNIT
45.4
68.1
49
°C/W
—
118.4
47.7
°C/W
—
—
7.2
°C/W
62.5
—
—
°C/W
9
—
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
RθJC follows MIL-STD-883, and RθJB follows JESD51.
(2)
6.6 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC = 2 V
1.9
1.998
VCC = 4.5 V
4.4
4.499
VCC = 6 V
5.9
5.999
IOH = –4 mA, VCC = 4.5 V
3.98
4.3
IOH= –5.2 mA, VCC = 6 V
5.48
5.8
IOH = –20 µA
VOH
VI = VIH or VIL
IOL = 20 µA
VOL
VI= VIH or VIL
MAX
UNIT
V
VCC = 2 V
0.002
0.1
VCC = 4.5 V
0.001
0.1
VCC = 6 V
V
0.001
0.1
IOL = 4 mA, VCC = 4.5 V
0.17
0.26
IOL = 5.2 mA, VCC = 6 V
0.15
0.26
±0.1
±100
nA
8
µA
3
10
pF
II
VI = VCC or 0, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
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6.7 Electrical Characteristics: SN74HC138
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IOH = –20 µA
VOH
VI = VIH or VIL
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
IOH = –4 mA, VCC = 4.5 V
IOL = 20 µA
VI= VIH or VIL
5.34
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
ICC
Ci
V
0.33
IOL = 5.2 mA, VCC = 6 V
VI = VCC or 0, VCC = 6 V
UNIT
V
5.9
IOL = 4 mA, VCC = 4.5 V
II
MAX
3.84
IOH= –5.2 mA, VCC = 6 V
VOL
TYP
0.33
±1000
nA
VI = VCC or 0, IO = 0, VCC = 6 V
80
µA
VCC = 2 V to 6 V
10
pF
MAX
UNIT
6.8 Electrical Characteristics: SN54HC138
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –20 µA
VOH
VI = VIH or VIL
MIN
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
5.9
IOH = –4 mA, VCC = 4.5 V
IOL = 20 µA
VI= VIH or VIL
V
3.7
IOH= –5.2 mA, VCC = 6 V
VOL
TYP
5.2
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
IOL = 4 mA, VCC = 4.5 V
0.4
IOL = 5.2 mA, VCC = 6 V
0.4
II
VI = VCC or 0, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
V
±1000
nA
160
µA
10
pF
6.9 Switching Characteristics
TA = 25°C and CL = 50 pF (unless otherwise noted; see Section 7)
PARAMETER
TEST CONDITIONS
From A, B, or C (input) to any Y (output)
tpd
From enable (input) to any Y (output)
tt
6
To any output
TYP
MAX
VCC = 2 V
MIN
67
180
VCC = 4.5 V
18
36
VCC = 6 V
15
31
VCC = 2 V
66
155
VCC = 4.5 V
18
31
VCC = 6 V
15
26
VCC = 2 V
38
75
VCC = 4.5 V
8
15
VCC = 6 V
6
13
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UNIT
ns
ns
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6.10 Switching Characteristics: SN74HC138
over recommended operating free-air temperature range and CL = 50 pF (unless otherwise noted; see Section 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC = 2 V
From A, B, or C (input) to any Y (output)
tpd
From enable (input) to any Y (output)
tt
To any output
MAX
UNIT
225
VCC = 4.5 V
45
VCC = 6 V
38
VCC = 2 V
195
VCC = 4.5 V
39
VCC = 6 V
33
VCC = 2 V
95
VCC = 4.5 V
19
VCC = 6 V
16
ns
ns
6.11 Switching Characteristics: SN54HC138
over recommended operating free-air temperature range and CL = 50 pF (unless otherwise noted; see Section 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC = 2 V
From A, B, or C (input) to any Y (output)
tpd
From enable (input) to any Y (output)
tt
To any output
MAX
UNIT
270
VCC = 4.5 V
54
VCC = 6 V
46
VCC = 2 V
235
VCC = 4.5 V
47
VCC = 6 V
40
VCC = 2 V
110
VCC = 4.5 V
22
VCC = 6 V
19
ns
ns
Propagation Delay From A, B, C to any Y (ns)
6.12 Typical Characteristic
70
65
60
55
50
45
40
35
30
25
20
15
2
2.5
3
3.5
4
4.5
Supply Voltage VCC (V)
5
5.5
6
D001
Figure 6-1. Typical Propagation Delay vs Supply Voltage
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7 Parameter Measurement Information
From Output
Under Test
VCC
Test
Point
Input
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
tPHL
90%
50%
10%
90%
tr
Input
50%
10%
90%
tPHL
VCC
90%
50%
10% 0 V
tr
Out-of-Phase
Output
90%
tPLH
50%
10%
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOH
50%
10%
VOL
tf
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SNx4HC138 devices are 3-to-8 decoders and demultiplexers. The three input pins, A, B, and C, select
which output is active. The selected output is pulled LOW, while the remaining outputs are all HIGH. The
conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low
and one active-high enable inputs reduce the requirement for external gates or inverters when expanding. A
24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing applications.
8.2 Functional Block Diagram
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
8.3 Feature Description
This device features three binary inputs to select a single active-low output. Three enable pins are also available
to enable or disable the outputs. One active high enable and two active low enable pins are available, and any
enable pin can be deactivated to force all outputs high. All three enable pins must be active for the output to be
enabled.
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8.4 Device Functional Modes
Table 8-1 lists the functions of the SNx4HC138 devices.
Table 8-1. Function Table
INPUTS
ENABLE
10
OUTPUTS
SELECT
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74HC138 is useful as a scanning column selector for an LED Matrix display as it can be used for the
low side drive of the LED string. The decoder functionality ensures that no more than one output is pulled to a
low-level logic voltage so that only a single column is enabled at any point in time.
9.2 Typical Application
SER
GPIO Inputs
SRCLK
QA
0V
RCLK
SN74HC595B
QH
3.3V
3.3V
HIGH
GPIO Inputs
A
Y0
HIGH B
0V
Y7
SN74HC138
HIGH C
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Figure 9-1. LED Matrix Driver Application
9.2.1 Design Requirements
These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light
loads, so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• For switch time specifications, see propagation delay times in Section 6.9.
• For input voltage level specifications for control inputs, see VIH and VIL in Section 6.6.
2. Recommended Output Conditions
• Outputs must not be pulled above VCC or below GND.
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9.2.3 Application Curve
5
VIH MIN
VIL MAX
4.5
Logic Level (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
2
2.4
2.8
3.2 3.6
4
4.4 4.8
Supply Voltage VCC (V)
5.2
5.6
6
D002
Figure 9-2. Input High and Input Low Thresholds vs Supply Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Section 6.3.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-µF bypass capacitor
is recommended to be placed close to the VCC terminal. It is acceptable to parallel multiple bypass capacitors
to reject different frequencies of noise; 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass
capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace (resulting in the reflection). It is a given that not all PCB traces can be straight, and so they have to turn
corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example maintains
constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 11-1. Trace Example
12
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN54HC138 SN74HC138
SN54HC138, SN74HC138
www.ti.com
SCLS107G – DECEMBER 1982 – REVISED OCTOBER 2021
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC138
Click here
Click here
Click here
Click here
Click here
SN74HC138
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN54HC138 SN74HC138
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8406201VEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8406201VE
A
SNV54HC138J
5962-8406201VFA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8406201VF
A
SNV54HC138W
84062012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84062012A
SNJ54HC
138FK
8406201EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8406201EA
SNJ54HC138J
Samples
8406201FA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8406201FA
SNJ54HC138W
Samples
JM38510/65802B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65802B2A
Samples
JM38510/65802BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65802BEA
Samples
M38510/65802B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65802B2A
Samples
M38510/65802BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65802BEA
Samples
SN54HC138J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC138J
Samples
SN74HC138D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DE4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HC138DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138DT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU | SN
N / A for Pkg Type
-40 to 85
SN74HC138N
Samples
SN74HC138NE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC138N
Samples
SN74HC138NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SN74HC138PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC138
Samples
SNJ54HC138FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84062012A
SNJ54HC
138FK
SNJ54HC138J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8406201EA
SNJ54HC138J
Samples
SNJ54HC138W
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8406201FA
SNJ54HC138W
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of