SN54HC148, SN74HC148
SCLS109H – APRIL 2004 – REVISED MARCH 2022
SNx4HC148 8-Line to 3-Line Priority Encoders
1 Features
3 Description
•
•
•
•
•
•
•
The SNx4HC148 is an 8-input priority encoder. Added
input enable (EI) and output enable (EO) signals allow
for cascading multiple stages without added external
circuitry.
Wide operating voltage range of 2V to 6V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 80-μA max ICC
Typical tpd = 16ns
±4-mA output drive at 5V
Low input current of 1μA max
Encode eight data lines to 3-line binary (Octal)
2 Applications
•
•
N-Bit encoding
Code converters and generators
(1)
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC148D
SOIC (16)
9.90 mm × 3.90 mm
SN74HC148N
PDIP (16)
19.31 mm × 6.35 mm
SN74HC148NS
SO (16)
10.20 mm × 5.30 mm
SN54HC148J
CDIP (16)
21.34 mm × 6.92 mm
SNJ54HC148FK
LCCC (20)
8.89 mm × 8.45 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC148, SN74HC148
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SCLS109H – APRIL 2004 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
(1)
6.2 Recommended Operating Conditions ..................... 4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Switching Characteristics ...........................................5
6.6 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Device Functional Modes............................................9
9 Application Information................................................ 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
12 Device and Documentation Support..........................12
12.1 Documentation Support.......................................... 12
12.2 Receiving Notification of Documentation Updates..12
12.3 Support Resources................................................. 12
12.4 Trademarks............................................................. 12
12.5 Electrostatic Discharge Caution..............................12
12.6 Glossary..................................................................12
13 Mechanical, Packaging, and Orderable
Information.................................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2004) to Revision H (March 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern datasheet standards.............................................................................................................................. 1
2
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SCLS109H – APRIL 2004 – REVISED MARCH 2022
5 Pin Configuration and Functions
J, D, N or NS Package
16-Pin CDIP, SOIC, PDIP, SO
Top View
FK Package
20-Pin LCCC
Top View
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
Supply voltage range
MIN
MAX
-0.5
7
)(2)
UNIT
V
IIK
Input clamp current
(VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current
(VO < 0 or VO > VCC)(2)
±20
mA
IO
Continuous output current
(VO = 0 to VCC)
±25
mA
VCC or GND
Continuous current through
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
6.2 Recommended Operating Conditions
SN54HC148
VCC
MIN
NOM
2
5
Supply voltage
VCC = 2V
VIH
High-level input voltage
VCC = 4.5V
SN74HC148
6
VI
Input voltage
VO
Output voltage
TA
(1)
5
6
3.15
4.2
4.2
VCC = 4.5V
0
0.5
0.5
1.35
0
VCC
0
V
VCC
V
VCC = 4.5V
500
500
VCC = 6V
400
400
125
V
VCC
1000
-55
V
1.8
VCC
1000
Operating free-air temperature
UNIT
V
1.35
1.8
0
VCC = 2V
Input transition rise/fall time
2
3.15
VCC = 6V
Δt/ΔVCC
MAX
1.5
VCC = 2V
Low-level input voltage
NOM
1.5
VCC = 6V
VIL
MIN
-40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
6.3 Thermal Information
THERMAL METRIC
R θJA
(1)
4
Junction-to-ambient thermal
resistance(1)
D (SOIC)
DW (SOIC)
N (PDIP)
NS (SO)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
73
57
67
64
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS109H – APRIL 2004 – REVISED MARCH 2022
6.4 Electrical Characteristics
TEST CONDITIONS(1)
PARAMETER
IOH = – 20 μA
VOH
High-level output voltage
IOH = – 4 mA
IOH = – 5.2 mA
VOL
VCC
TA = 25°C
SN54HC148
MAX
MIN
SN74HC148
MIN
TYP
MAX
MIN
2
1.9
1.998
1.9
1.9
4.5
4.4
4.499
4.4
4.4
6
5.9
5.999
5.9
5.9
4.5
3.98
4.3
3.7
3.84
6
5.48
5.8
5.2
5.34
MAX
V
2
0.002
0.1
0.1
0.1
IOL = 20 μA
4.5
0.001
0.1
0.1
0.1
6
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5
0.17
0.26
0.4
0.33
Low-level output voltage
UNIT
V
IOL = 5.2 mA
6
0.15
0.26
0.4
0.33
II
Input hold current
VI = VCC or 0
6
±0.1
±100
±1000
±1000
nA
ICC
Supply current
VI = VCC or 0. IO = 0
8
160
80
μA
Ci
Input capacitance
3
10
10
10
pF
(1)
6
2 to 6
VI = VIH or VIL, unless otherwise noted.
6.5 Switching Characteristics
CL = 50pF, unless otherwise specified. See (Parameter Measurement Information)
FROM
(INPUT)
PARAMETER
1-7
TO
(OUTPUT)
A0, A1, A2
EO
0-7
GS
tpd
Propagation Dealy
A0, A1, A2
EI
GS
EO
tt
Transition time
Any
VCC
TA = 25°C
MIN
SN54HC148
MIN
MAX
SN74HC148
TYP
MAX
MIN
MAX
2
69
180
270
225
4.5
23
36
54
45
6
21
31
46
38
2
60
150
225
190
4.5
20
30
45
38
6
17
26
38
33
2
75
190
285
240
4.5
25
38
57
48
6
21
32
48
41
2
78
195
295
245
4.5
26
39
59
49
6
22
33
50
42
2
57
145
220
180
4.5
19
29
44
36
6
16
25
38
31
2
66
165
250
205
4.5
22
33
50
41
6
19
28
43
35
2
28
75
110
95
4.5
8
15
22
19
6
6
13
19
16
UNIT
ns
ns
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SCLS109H – APRIL 2004 – REVISED MARCH 2022
6.6 Operating Characteristics
TA = 25°C
Cpd
6
Power dissipation capacitance
Test Conditions
TYP
UNIT
No load
35
pF
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
VOL
tPLH(1)
VOH
Output
50%
0V
tf(1)
90%
VOH
90%
Output
50%
tPHL(1)
VCC
90%
Input
50%
50%
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
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8 Detailed Description
8.1 Overview
The ’HC148 devices feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. These devices encode eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input
EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry.
Data inputs and outputs are active at the low logic level.
8.2 Functional Block Diagram
8
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8.3 Device Functional Modes
Table 8-1. Function Table
INPUTS
OUTPUTS
EI
0
1
2
3
4
5
6
7
A2
A1
A0
GS
EO
H
X
X
X
X
X
X
X
X
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
X
L
L
L
L
L
H
L
X
X
X
X
X
X
L
H
L
L
H
L
H
L
X
X
X
X
X
L
H
H
L
H
L
L
H
L
X
X
X
X
L
H
H
H
L
H
H
L
H
L
X
X
X
L
H
H
H
H
H
L
L
L
H
L
X
X
L
H
H
H
H
H
H
L
H
L
H
L
X
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
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9 Application Information
Figure 9-1. Priority Encoder for 16 Bits
Because the ’HC148 devices are combinational logic circuits, wrong addresses can appear during input
transients. Moreover, a change from high to low at EI can cause a transient low on GS when all inputs are
high. This must be considered when strobing the outputs.
10
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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10-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN54HC148J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC148J
Samples
SN74HC148D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DE4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148DT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SN74HC148N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC148N
Samples
SN74HC148NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC148
Samples
SNJ54HC148FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SNJ54HC
148FK
Samples
SNJ54HC148J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SNJ54HC148J
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of