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SN74HC14-Q1
SCLS532B – AUGUST 2003 – REVISED APRIL 2020
SN74HC14-Q1 Automotive Hex Inverters with Schmitt-Trigger Inputs
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1:
–40°C to +125°C, TA
Schmitt-trigger inputs allow for slow or noisy input
signals
Positive and negative input clamp diodes
Wide operating voltage range: 2 V to 6 V
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
Synchronize inverted clock inputs
Debounce a switch
Invert a digital signal
3 Description
This device contains six independent inverters with
Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A in positive logic.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC14QDRQ1
SOIC (14)
8.70 mm × 3.90 mm
SN74HC14QPWRQ1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional pinout of the SN74HC14-Q1
1A
1
14
1Y
2
13
6A
2A
3
4
12
11
6Y
3A
5
10
5Y
3Y
6
7
9
8
4A
2Y
GND
VCC
5A
4Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HC14-Q1
SCLS532B – AUGUST 2003 – REVISED APRIL 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
4
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2008) to Revision B
Page
•
Updated to new data sheet standards.................................................................................................................................... 1
•
Changed RθJA for PW package from 113 °C/W to 151.7 °C/W .............................................................................................. 4
•
Changed RθJA for D package from 86 °C/W to 133.6 °C/W ................................................................................................... 4
2
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5 Pin Configuration and Functions
D or PW Package
14-Pin SOIC or TSSOP
Top View
1A
1
14
VCC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Pin Functions
PIN
NAME
I/O
NO.
1A
1
Input
1Y
2
Output
2A
3
Input
2Y
4
Output
3A
5
Input
3Y
6
Output
GND
7
—
4Y
8
Output
4A
9
Input
5Y
10
Output
5A
11
Input
6Y
12
Output
6A
13
Input
VCC
14
—
DESCRIPTION
Channel 1, Input A
Channel 1, Output Y
Channel 2, Input A
Channel 2, Output Y
Channel 3, Input A
Channel 3, Output Y
Ground
Channel 4, Output Y
Channel 4, Input A
Channel 5, Output Y
Channel 5, Input A
Channel 6, Output Y
Channel 6, Input A
Positive Supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature (3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2000
Charged device model (CDM), per AEC Q100011 CDM ESD Classification Level C6
±1000
UNIT
V
AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
TA
Operating free-air temperature
MIN
NOM
MAX
2
5
6
V
1.8
V
0
VCC
V
0
VCC
V
–40
125
°C
VCC = 6 V
SN74HC132-Q1
UNIT
6.4 Thermal Information
SN74HC14-Q1
THERMAL METRIC
PW (TSSOP)
D (SOIC)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
151.7
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.4
89.0
°C/W
RθJB
Junction-to-board thermal resistance
94.7
89.5
°C/W
ΨJT
Junction-to-top characterization parameter
25.2
45.5
°C/W
ΨJB
Junction-to-board characterization parameter
94.1
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
4
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
VT+
VT-
ΔVT
TEST CONDITIONS
VCC
2V
Positive
switching
threshold
Negative
switching
threshold
Hysteresis (VT+ VT-)
High-level output VI = VIH
voltage
or VIL
Low-level output
voltage
MIN
TYP
UNIT
MAX
1.2
1.5
0.7
1.5
2.5
3.15
1.55
3.15
6V
2.1
3.3
4.2
2.1
4.2
2V
0.3
0.6
1
0.3
1
4.5 V
0.9
1.6
2.45
0.9
2.45
6V
1.2
2
3.2
1.2
3.2
2V
0.2
0.6
1.2
0.2
1.2
4.5 V
0.4
0.9
2.1
0.4
2.1
6V
0.5
1.3
2.5
0.5
2.5
2V
1.9
1.998
1.9
4.5 V
4.4
4.499
4.4
6V
5.9
5.999
5.9
3.7
4.5 V
3.98
4.3
IOH = -5.2 mA
6V
5.48
5.8
VI = VIH
or VIL
-40°C to 125°C
MAX
0.7
IOH = -4 mA
IOL = 20 µA
VOL
TYP
1.55
4.5 V
IOH = -20 µA
VOH
25°C
MIN
V
V
V
V
5.2
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
6V
0.001
0.1
0.1
V
IOL = 4 mA
4.5 V
0.17
0.26
0.4
IOL = 5.2 mA
6V
0.15
0.26
0.4
±0.1
±100
±1000
nA
2
40
µA
10
10
pF
II
Input leakage
current
VI = VCC or 0
6V
ICC
Supply current
VI = VCC
or 0
6V
Ci
Input
capacitance
IO = 0
5V
3
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted), CL = 50 pF
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
tpd
tt
Propagation delay
A
Transition-time
Y
Y
–40°C to 125°C
MIN
TYP
UNIT
TYP
MAX
MAX
2V
55
125
190
4.5 V
12
25
38
6V
11
21
32
2V
38
75
110
4.5 V
8
15
22
6V
6
13
19
ns
ns
6.7 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST CONDITIONS
No load
MIN
TYP
MAX
20
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UNIT
pF
5
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6.8 Typical Characteristics
TA = 25°C
7
0.15
6
VOH Output High Voltage (V)
VOL Output Low Voltage (V)
0.135
0.12
0.105
0.09
0.075
0.06
0.045
0.03
2V
4.5 V
6V
0.015
5
4
3
2
2V
4.5 V
6V
1
0
0
0
0.0009
0.0018 0.0027 0.0036 0.0045
IOL Output Low Current (mA)
0
0.0054
0.001
0.002
0.003
0.004
IOH Output High Current (mA)
D001
Figure 1. Output voltage versus output current in low state
0.005
0.006
D002
Figure 2. Output voltage versus output current in high state
7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
The outputs are measured one at a time, with one input transition per measurement.
Test
Point
90%
VCC
90%
Input
10%
10%
tr(1)
From Output
Under Test
CL(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
CL= 50 pF and includes probe and jig capacitance.
Figure 3. Load Circuit
tf(1)
VOL
Figure 4. Voltage Waveforms
Transition Times
VCC
Input
50%
50%
0V
tPHL(1)
tPLH(1)
VOH
Output
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
The maximum between tPLH and TPHL is used for tpd.
Figure 5. Voltage Waveforms
Propagation Delays
6
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8 Detailed Description
8.1 Overview
This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean
function Y = A in positive logic.
8.2 Functional Block Diagram
xA
xY
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
The SN74HC14-Q1 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF. If larger capacitive loads are required, it is
recommended to add a series resistor between the output and the capacitor to limit output current to the values
given in the Absolute Maximum Ratings.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated
with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage
current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
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Feature Description (continued)
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 6.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The recommended input and output voltage ratings may
be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1. Function Table
8
INPUT
OUTPUT
A
Y
L
H
H
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HC14-Q1 can be used to add an additional stage to a counter with an external flip-flop. Because
counters use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. This
function only requires one of the six available inverters in the SN74HC14-Q1 device, so the remaining channels
can be used for other applications needing an inverted signal or improved signal integrity. Unused inputs must be
terminated at VCC or GND. Unused outputs can be left floating.
9.2 Typical Application
20
Counter
Clear
21
CLR
22
23
Input
CLR
Q
24
D-Typ e
Flip-Flop
D
Q
Figure 7. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC14-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device can
only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to
exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
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Typical Application (continued)
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC14-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC14-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC14Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Input ± 32 kHz
23
24 ± 1 kHz
23
24
Figure 8. Application timing diagram
10
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 9.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Unused input
tied to GND
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
1Y
2
13
VCC Unused input
tied to VCC
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Unused output
left floating
Figure 9. Example layout for the SN74HC14-Q1
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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21-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HC14QDRG4Q1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC14QQ1
SN74HC14QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC14QQ1
SN74HC14QPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC14QQ1
SN74HC14QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC14QQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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