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SN54HC165, SN74HC165
SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
SNx4HC165 8-Bit Parallel-Load Shift Registers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The SNx4HC165 devices are 8-bit parallel-load shift
registers that, when clocked, shift the data toward a
serial (QH) output. Parallel-in access to each stage is
provided by eight individual direct data (A−H) inputs
that are enabled by a low level at the shift/load
(SH/LD) input. The SNx4HC165 devices also feature
a clock-inhibit (CLK INH) function and a
complementary serial (QH) output.
1
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Clocking is accomplished by a low-to-high transition
of the clock (CLK) input while SH/LD is held high and
CLK INH is held low. The functions of CLK and CLK
INH are interchangeable. Because a low CLK and a
low-to-high transition of CLK INH also accomplish
clocking, CLK INH must be changed to the high level
only while CLK is high. Parallel loading is inhibited
when SH/LD is held high. While SH/LD is low, the
parallel inputs to the register are enabled
independently of the levels of the CLK, CLK INH, or
serial (SER) inputs.
2 Applications
•
•
•
•
•
Device Information(1)
Programable Logic Controllers
Appliances
Video Display Systems
Output Expander
Keyboards
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC165D
SOIC (16)
10.00 mm × 6.20 mm
SN74HC165DB
SSOP (16)
8.20 mm × 6.50 mm
SN74HC165N
PDIP (16)
6.60 mm × 18.92 mm
SN74HC165NS
SO (16)
8.20 mm × 9.90 mm
SN74HC165PW
TSSOP (16)
6.60 mm × 5.10 mm
SN54HC165FK
LCCC (20)
9.09 mm × 9.09 mm
SN54HC165J
CDIP (16)
21.34 mm × 7.52 mm
SN54HC165W
CFP (16)
9.40 mm × 7.75 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram Positive Logic
A
SH/LD
CLK INH
CLK
SER
1
B
11
C
12
D
13
E
14
F
G
4
3
H
5
6
9
15
QH
2
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
7
QH
Pin numbers shown are for theD, DB, J, N, NS, PW, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC165, SN74HC165
SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics, TA = 25°C ........................ 5
Electrical Characteristics, SN54HC165 .................... 5
Electrical Characteristics, SN74HC165 .................... 5
Switching Characteristics, TA = 25°C........................ 6
Switching Characteristics, SN54HC165.................... 6
Switching Characteristics, SN74HC165.................. 7
Timing Requirements, TA = 25°C............................ 7
Timing Requirements, SN54HC165........................ 8
Timing Requirements, SN74HC165 ....................... 9
Operating Characteristics...................................... 10
Typical Characteristics .......................................... 11
7
8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Table .........................................
12
12
13
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2013) to Revision H
Page
•
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added ESD warning. ............................................................................................................................................................ 16
Changes from Revision F (December 2010) to Revision G
Page
•
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Extended maximum temperature operating range from 85°C to 125°C................................................................................. 4
2
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Copyright © 1982–2015, Texas Instruments Incorporated
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
D, DB, N, NS, J, W, or PW Package
16-Pin SOIC, SSOP, PDIP, SO, CDIP, CFP, or TSSOP
Top View
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CLK
SH/LD
NC
VCC
CLK INH
1
VCC
CLK INH
D
C
B
A
SER
QH
E
F
NC
G
H
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
D
C
NC
B
A
QH
GND
NC
QH
SER
SH/LD
CLK
E
F
G
H
QH
GND
FK Package
20-Pin LCCC
Top View
Pin Functions (1)
PIN
I/O
DESCRIPTION
D, DB, N, NS,
PW, J or W
FK
A
11
14
I
Parallel Input
B
12
15
I
Parallel Input
C
13
17
I
Parallel Input
CLK
2
3
I
Clock input
CLK INH
15
19
I
Clock Inhibit, when High No change in output
D
14
18
I
Parallel Input
E
3
4
I
Parallel Input
F
4
5
I
Parallel Input
G
5
7
I
Parallel Input
GND
8
10
—
H
6
8
I
NAME
Ground Pin
Parallel Input
1
NC
—
6
11
—
Not Connected
16
QH
9
12
O
Serial Output
QH
7
9
O
Complementary Serial Output
SER
10
13
I
Serial Input
SH/LD
1
2
I
Shift or Load input, When High Data, shifted. When Low data is
loaded from parallel inputs
VCC
16
20
—
(1)
Power Pin
NC – No internal connection
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SN54HC165, SN74HC165
SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
±1500
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
MIN
NOM
MAX
2
5
6
3.15
V
4.2
VCC = 2 V
Low level input voltage
0.5
VCC = 4.5 V
1.35
VCC = 6 V
VI
Input voltage
VO
Output voltage
0
0
Input transition rise and fall time
VCC = 4.5 V
(1)
(2)
Operating free-air temperature
VCC
V
VCC
V
1000
500
VCC = 6 V
TA
V
1.8
VCC = 2 V
Δt/Δv (2)
V
1.5
VCC = 4.5 V
VCC = 6 V
VIL
UNIT
ns/V
400
SN54HC165
–55
125
SN74HC165
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
6.4 Thermal Information
SN74HC165
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
D (SOIC)
DB (SSOP)
N (DIP)
NS (SO)
PW (TSSOP)
73
82
67
64
108
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
6.5 Electrical Characteristics, TA = 25°C
over recommended operating free-air temperature range for both the SN74HC165 and SN54HC165 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
VOL
VI = VCC or 0
VI = VCC or 0,
TYP
2V
1.9
1.998
4.5 V
4.4
4.499
6V
5.9
5.999
4.5 V
3.98
4.3
6V
5.48
MAX
UNIT
V
5.8
0.002
0.1
IOL = 20 µA
4.5 V
0.001
0.1
6V
0.001
0.1
IOL = 4 mA
4.5 V
0.17
0.26
6V
0.15
0.26
6V
±0.1
±100
nA
8
µA
10
pF
IOL = 5.2 mA
ICC
MIN
2V
VI = VIH or VIL
II
VCC
IO = 0
6V
Ci
2 V to 6 V
3
V
6.6 Electrical Characteristics, SN54HC165
over recommended operating free-air temperature range, TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
MIN
2V
1.9
IOH = –20 µA
4.5 V
4.4
6V
5.9
IOH = –4 mA
4.5 V
3.7
6V
5.2
VI = VIH or VIL
IOH = –5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
VI = VCC or 0
ICC
VI = VCC or 0,
IO = 0
Ci
TYP
MAX
UNIT
V
2V
0.1
4.5 V
0.1
6V
0.1
4.5 V
0.4
V
6V
0.4
6V
±1000
nA
6V
160
µA
2 V to 6 V
10
pF
6.7 Electrical Characteristics, SN74HC165
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20 µA
VOL
TA = –40°C to 125°C
TA = –40°C to 85°C
VCC
MIN
2V
1.9
4.5 V
4.4
6V
5.9
4.5 V
3.84
6V
5.34
TA = –40°C to 125°C
TA = –40°C to 85°C
VI = VIH or VIL
MAX
UNIT
V
3.7
TA = –40°C to 125°C
TA = –40°C to 125°C
TYP
5.2
2V
0.1
4.5 V
0.1
6V
0.1
IOL = 4 mA
TA = –40°C to 125°C
4.5 V
0.33
IOL = 5.2 mA
TA = –40°C to 125°C
6V
0.33
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Electrical Characteristics, SN74HC165 (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
II
TEST CONDITIONS
VI = VCC or 0
VCC
TA = –40°C to 125°C
TA = –40°C to 85°C
ICC
VI = VCC or 0,
IO = 0
Ci
Recommended TA = –40°C to 125°C
MIN
TYP
MAX
UNIT
6V
±1000
nA
6V
80
TA = –40°C to 125°C
µA
160
2 V to 6 V
10
pF
6.8 Switching Characteristics, TA = 25°C
over recommended operating free-air temperature range for both the SN74HC165 and SN54HC165, CL = 50 pF (unless
otherwise noted) (see Figure 2)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
fmax
SH/LD
tpd
QH or QH
CLK
QH or QH
H
QH or QH
tt
Any
VCC
MIN
TYP
2V
6
13
4.5 V
31
50
6V
36
62
MAX
UNIT
MHz
2V
80
150
4.5 V
20
30
6V
16
26
2V
75
150
4.5 V
15
30
6V
13
26
2V
75
150
4.5 V
15
30
6V
13
26
2V
38
75
4.5 V
8
15
6V
6
13
ns
ns
6.9 Switching Characteristics, SN54HC165
over recommended operating free-air temperature range, TA = –55°C to 125°C, CL = 50 pF (unless otherwise noted) (see
Figure 2)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
fmax
SH/LD
tpd
CLK
H
tt
6
QH or QH
QH or QH
QH or QH
Any
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VCC
MIN
2V
4.2
4.5 V
21
6V
25
MAX
UNIT
MHz
2V
225
4.5 V
45
6V
38
2V
225
4.5 V
45
6V
38
2V
225
4.5 V
45
6V
38
2V
110
4.5 V
22
6V
19
ns
ns
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
6.10 Switching Characteristics, SN74HC165
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO (OUTPUT)
VCC
2V
4.5 V
fmax
6V
2V
SH/LD
QH or QH
4.5 V
6V
2V
tpd
CLK
QH or QH
4.5 V
6V
2V
H
QH or QH
4.5 V
6V
2V
tt
Any
4.5 V
6V
TEMPERATURE
MIN
TA = –40°C to 85°C
MAX
UNIT
5
TA = –40°C to 125°C
4.2
TA = –40°C to 85°C
25
TA = –40°C to 125°C
21
TA = –40°C to 85°C
29
TA = –40°C to 125°C
25
MHz
TA = –40°C to 85°C
190
TA = –40°C to 125°C
225
TA = –40°C to 85°C
38
TA = –40°C to 125°C
45
TA = –40°C to 85°C
32
TA = –40°C to 125°C
38
TA = –40°C to 85°C
190
TA = –40°C to 125°C
225
TA = –40°C to 85°C
38
TA = –40°C to 125°C
45
TA = –40°C to 85°C
32
TA = –40°C to 125°C
38
TA = –40°C to 85°C
190
TA = –40°C to 125°C
225
TA = –40°C to 85°C
38
TA = –40°C to 125°C
45
TA = –40°C to 85°C
32
TA = –40°C to 125°C
38
TA = –40°C to 85°C
95
TA = –40°C to 125°C
110
TA = –40°C to 85°C
19
TA = –40°C to 125°C
22
TA = –40°C to 85°C
16
TA = –40°C to 125°C
19
ns
ns
6.11 Timing Requirements, TA = 25°C
over recommended operating free-air temperature range for both the SN74HC165 and SN54HC165 (unless otherwise noted)
VCC
fclock
Clock frequency
SH/LD low
tw
Pulse duration
CLK high or low
MIN
MAX
2V
6
4.5 V
31
6V
36
2V
80
4.5 V
16
6V
14
2V
80
4.5 V
16
6V
14
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UNIT
MHz
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ns
7
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
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Timing Requirements, TA = 25°C (continued)
over recommended operating free-air temperature range for both the SN74HC165 and SN54HC165 (unless otherwise noted)
SH/LD high before CLK↑
SER before CLK↑
tsu
Set-up time
CLK INH low before CLK↑
CLK INH high before CLK↑
Data before SH/LD↓
SER data after CLK↑
th
Hold time
PAR data after SH/LD↓
VCC
MIN
2V
80
4.5 V
16
6V
14
2V
40
4.5 V
8
6V
7
2V
100
4.5 V
20
6V
17
2V
40
4.5 V
8
6V
7
2V
100
4.5 V
20
6V
17
2V
5
4.5 V
5
6V
5
2V
5
4.5 V
5
6V
5
MAX
UNIT
ns
ns
6.12 Timing Requirements, SN54HC165
over recommended operating free-air temperature range, TA = –55°C to 125°C (unless otherwise noted)
VCC
fclock
Clock frequency
SH/LD low
tw
Pulse duration
CLK high or low
8
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MIN
MAX
2V
4.2
4.5 V
21
6V
25
2V
120
4.5 V
24
6V
20
2V
120
4.5 V
24
6V
20
UNIT
MHz
ns
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
Timing Requirements, SN54HC165 (continued)
over recommended operating free-air temperature range, TA = –55°C to 125°C (unless otherwise noted)
SH/LD high before CLK↑
SER before CLK↑
tsu
Set-up time
CLK INH low before CLK↑
CLK INH high before CLK↑
Data before SH/LD↓
SER data after CLK↑
th
Hold time
PAR data after SH/LD↓
VCC
MIN
2V
120
4.5 V
24
6V
20
2V
60
4.5 V
12
6V
10
2V
150
4.5 V
30
6V
25
2V
60
4.5 V
12
6V
10
2V
150
4.5 V
30
6V
26
2V
5
4.5 V
5
6V
5
2V
5
4.5 V
5
6V
5
MAX
UNIT
ns
ns
6.13 Timing Requirements, SN74HC165
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
2V
fclock
4.5 V
Clock frequency
6V
TEMPERATURE
MIN
TA = –40°C to 85°C
SH/LD low
4.5 V
6V
tw
Pulse duration
2V
CLK high or low
4.5 V
6V
TA = –40°C to 125°C
4.2
TA = –40°C to 85°C
25
TA = –40°C to 125°C
21
TA = –40°C to 85°C
29
100
TA = –40°C to 125°C
120
TA = –40°C to 85°C
20
TA = –40°C to 125°C
24
TA = –40°C to 85°C
17
TA = –40°C to 125°C
20
TA = –40°C to 85°C
100
TA = –40°C to 125°C
120
TA = –40°C to 85°C
20
TA = –40°C to 125°C
24
TA = –40°C to 85°C
17
TA = –40°C to 125°C
20
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MHz
25
TA = –40°C to 85°C
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UNIT
5
TA = –40°C to 125°C
2V
MAX
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Timing Requirements, SN74HC165 (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
2V
SH/LD high
before CLK↑
4.5 V
6V
2V
SER before
CLK↑
4.5 V
6V
2V
tsu
Set-up time
CLK INH low
before CLK↑
4.5 V
6V
2V
CLK INH high
before CLK↑
4.5 V
6V
2V
Data before
SH/LD↓
4.5 V
6V
SER data after
CLK↑
th
Hold time
PAR data after
SH/LD↓
TEMPERATURE
MIN
TA = –40°C to 85°C
100
TA = –40°C to 125°C
120
TA = –40°C to 85°C
20
TA = –40°C to 125°C
24
TA = –40°C to 85°C
17
TA = –40°C to 125°C
20
TA = –40°C to 85°C
50
TA = –40°C to 125°C
60
TA = –40°C to 85°C
10
TA = –40°C to 125°C
12
TA = –40°C to 85°C
9
TA = –40°C to 125°C
10
TA = –40°C to 85°C
125
TA = –40°C to 125°C
150
TA = –40°C to 85°C
25
TA = –40°C to 125°C
30
TA = –40°C to 85°C
21
TA = –40°C to 125°C
25
TA = –40°C to 85°C
50
TA = –40°C to 125°C
60
TA = –40°C to 85°C
10
TA = –40°C to 125°C
12
TA = –40°C to 85°C
9
TA = –40°C to 125°C
10
TA = –40°C to 85°C
125
TA = –40°C to 125°C
150
TA = –40°C to 85°C
25
TA = –40°C to 125°C
30
TA = –40°C to 85°C
21
TA = –40°C to 125°C
26
2V
TA = –40°C to 125°C
5
4.5 V
TA = –40°C to 125°C
5
6V
TA = –40°C to 125°C
5
2V
TA = –40°C to 125°C
5
4.5 V
TA = –40°C to 125°C
5
6V
TA = –40°C to 125°C
5
MAX
UNIT
ns
ns
6.14 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
10
TEST CONDITIONS
Power dissipation capacitance
Submit Documentation Feedback
No load
TYP
75
UNIT
pF
Copyright © 1982–2015, Texas Instruments Incorporated
Product Folder Links: SN54HC165 SN74HC165
SN54HC165, SN74HC165
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
6.15 Typical Characteristics
80
P r o p a g a tio n D e la y T p d ( n s )
70
60
50
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply Voltage (V)
6.5
D001
Figure 1. Propagation Delay vs Supply Voltage at TA = 25°C
7 Parameter Measurement Information
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
VCC
Input
50%
50%
0V
tPLH
VCC
Reference
Input
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
50%
10%
Out-of-Phase
Output
VOH
50%
10%
VOL
tf
tPLH
90%
50%
10%
50%
10%
90%
tf
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90%
tr
th
90%
tPHL
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 1982–2015, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The SNx4HC165 is an 8-bit Parallel load shift register with 1 serial input and 8 parallel load input. The device
loads all the 8 bits simultaneously through parallel load input when SH/LD is low. This will also ignore any input
at CLK or CLK INH.
The device shifts the data when CLK toggles. The data is shifted on rising edge of the clock. Clock Inhibit (CLK
INH) inhibits the clock function resulting in no change of the output. If SH/LD is low clock inputs are ignored. To
realize the shift function, SH/LD should be high.
CLK and CLK INH functions are interchangeable. If CLK is low then change a clock signal at CLK INH pin
causes a shift of data to QH. If CLK INH is Low clock signal on CLK pin shifts the data out to QH.
8.2 Functional Block Diagram
A
SH/LD
CLK INH
CLK
SER
1
B
11
C
12
D
13
E
14
F
G
4
3
H
5
6
9
15
QH
2
S
C1
1D
R
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
7
QH
Pin numbers shown are for theD, DB, J, N, NS, PW, and W packages.
Figure 3. Logic Diagram Positive Logic
CLK
CLK INH
SER
L
SH/LD
Data
Inputs
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
QH
H
H
L
H
L
H
L
H
QH
L
L
H
L
H
L
H
L
Inhibit
Serial Shift
Load
Figure 4. Typical Shift, Load, and Inhibit Sequence
12
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SN54HC165, SN74HC165
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
8.3 Feature Description
The SNx4HC165 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads
and Low Power Consumption, 80-μA maximum I. It is typically tpd = 13 ns and has ±4-mA output drive at 5 V with
low input current of 1-μA maximum. The device features the direct overloading load of data input, meaning
parallel data is loaded irrespective of clock signals.
8.4 Device Functional Table
Table 1 lists the functional modes of the SNx4HC165.
Table 1. Function Table
INPUTS
SH/LD
(1)
CLK
CLK INH
FUNCTION
L
X
X
Parallel load
H
H
X
No change
H
X
H
No change
H
L
↑
Shift (1)
H
↑
L
Shift (1)
Shift : Content of each internal register shifts towards serial output QH. Data at SER is shifted into the first register
Copyright © 1982–2015, Texas Instruments Incorporated
Product Folder Links: SN54HC165 SN74HC165
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4HC165 is an 8-bit shift register that can be used as a serializer in order to reduce the number of
connection needed when transmitting signals between boards or to the device. SNx4HC165 can be used to
expand inputs for processors with limited GPIOs for examples basic keyboard interface to the controller.
SNx4HC165 allows inputs to be load into the shift registers and clock is used to shift data to the processor.
Multiple SNx4HC165 can be cascaded together to allow more digital inputs to be interfaced with single processor
by connecting output of the cascaded shift register QH to serial input SER of the SNx4HC165 and so on. Note
this application does not allow the communication to be bi-direction in nature as data can only be read by the
processor not written back.
9.2 Typical Application
2
2
15
15
From other shift register
10
10
1
11
11
7
12
Digital
Inputs /
Keyboard
13
9
13
VCC
16
4
0.1µF
5
9
3
16
4
Controller,
Processor
14
Data
Data
VCC
3
7
12
Digital
Inputs /
Keyboard
14
1
5
8
0.1 µF
8
6
6
Figure 5. Typical Application Diagram for SN74HC165
9.2.1 Design Requirements
Ensure that the incoming clock rising edge meets the criteria in Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
Ensure that input and output voltages do not exceed ratings in Absolute Maximum Ratings.
Input voltage threshold information for each device can be found in the Electrical Characteristics tables in the
Specifications section.
Detailed timing requirements for each device can be found in Timing Requirements tables in the Specifications
section.
14
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
Typical Application (continued)
9.2.3 Application Curve
80
P r o p a g a tio n D e la y T p d ( n s )
70
60
50
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply Voltage (V)
6.5
D001
Figure 6. Propagation Delay vs Supply Voltage at TA = 25°C
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor in order to prevent power disturbance. For devices with a
single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 7 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 7. Trace Example
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SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Implications of Slow or Floating CMOS Inputs, SCBA004.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC165
Click here
Click here
Click here
Click here
Click here
SN74HC165
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
84095012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84095012A
SNJ54HC
165FK
8409501EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409501EA
SNJ54HC165J
8409501FA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409501FA
SNJ54HC165W
SN54HC165J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC165J
SN74HC165D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DRG3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165DT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
N / A for Pkg Type
-40 to 125
SN74HC165N
SN74HC165NE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74HC165N
SN74HC165NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC165PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165PWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SN74HC165PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC165
SNJ54HC165FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84095012A
SNJ54HC
165FK
SNJ54HC165J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409501EA
SNJ54HC165J
SNJ54HC165W
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409501FA
SNJ54HC165W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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