SN74HC174PWT

SN54HC174, SN74HC174 SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 SNx4HC174 Hex D-Type Flip-Flops with Clear 1 Features 3 Description • • • • • • • The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR) inputs. Wide operating voltage range of 2 V to 6 V Outputs can drive up to 10 LSTTL loads Low power consumption, 80-μA max ICC Typical tpd = 14 ns ±4-mA output drive at 5 V Low input current of 1 μA max Contain six flip-flops with single-rail 2 Applications • • • Buffer/storage registers Shift registers Pattern generators Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC174D SOIC (16) 9.90 mm × 3.90 mm SN74HC174DB SSOP (16) 6.20 mm × 5.30 mm SN74HC174N PDIP (16) 19.31 mm × 6.35 mm SN74HC174NS SO (16) 6.20 mm × 5.30 mm SN74HC174PW TSSOP (16) 5.00 mm × 4.40 mm SN54HC174J CDIP (16) 24.38 mm × 6.92 mm SNJ54HC174FK LCCC (20) 8.89 mm × 8.45 mm SNJ54HC174W CFP (16) 10.16 mm × 6.73 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 Recommended Operating Conditions(1) .................... 4 6.3 Thermal Information....................................................4 6.4 Electrical Characteristics.............................................5 6.5 Timing Requirements ................................................. 5 6.6 Switching Characteristics ...........................................6 6.7 Operating Characteristics........................................... 6 7 Parameter Measurement Information............................ 7 8 Detailed Description........................................................8 8.1 Overview..................................................................... 8 8.2 Functional Block Diagram........................................... 8 8.3 Device Functional Modes............................................8 9 Power Supply Recommendations..................................9 10 Layout.............................................................................9 10.1 Layout Guidelines..................................................... 9 11 Device and Documentation Support..........................10 11.1 Receiving Notification of Documentation Updates.. 10 11.2 Support Resources................................................. 10 11.3 Trademarks............................................................. 10 11.4 Electrostatic Discharge Caution.............................. 10 11.5 Glossary.................................................................. 10 12 Mechanical, Packaging, and Orderable Information.................................................................... 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2003) to Revision E (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 5 Pin Configuration and Functions J, W, D, DB, N, NS, or PW Package 16-Pin CDIP, CFP, SOIC, SSOP, PDIP, SO, TSSOP Top View FK Package 20-PIn LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 3 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range current(2) MIN MAX -0.5 7 UNIT V IIK Input clamp VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C 150 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature (1) (2) –65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 Recommended Operating Conditions(1) SN54HC174 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V SN74HC174 MIN NOM MAX 2 5 6 Low-level input voltage VI Input voltage VO Output voltage 5 6 3.15 4.2 4.2 VCC = 4.5 V 0 Input transition rise/fall time VCC = 4.5 V Operating free-air temperature −55 0.5 0.5 1.35 1.35 V V 1.8 VCC 0 VCC 0 VCC V VCC V 1000 1000 500 500 400 400 125 UNIT V 1.8 0 VCC = 6 V (1) 2 3.15 VCC = 2 V TA MAX 1.5 VCC = 6 V Δt/Δv NOM 1.5 VCC = 2 V VIL MIN −40 85 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal (1) resistance D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS UNIT 73 82 67 64 108 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 6.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST (1) CONDITIONS VCC (V) IOH = −20 μA VOH IOH = −4 mA IOH = −5.2 mA ICC MAX MIN SN74HC174 MIN TYP MAX MIN 2 1.9 1.998 1.9 1.9 4.5 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 3.98 4.3 3.7 3.84 6 5.48 5.8 5.2 5.34 MAX UNIT V 2 0.002 0.1 0.1 0.1 4.5 0.001 0.1 0.1 0.1 6 0.001 0.1 0.1 0.1 IOL = 4 mA 4.5 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 0.15 0.26 0.4 0.33 VI = VCC or 0 6 ±0.1 ±100 ±1000 ±1000 nA VI = VCC or 0, IO =0 6 8 160 80 μA 10 10 10 pF Ci (1) SN54HC174 IOL = 20 μA VOL II TA = 25°C 2 to 6 3 V VI = VIH or VIL, unless otherwise noted. 6.5 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) VCC (V) fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ CLR inactive th Hold time, data after CLK↑ TA = 25°C MIN SN54HC174 MAX MIN SN74HC174 MAX MIN MAX 2 6 4.2 5 4.5 31 21 25 6 36 25 29 2 80 120 100 4.5 16 24 20 6 14 20 17 2 80 120 100 4.5 16 24 20 6 14 20 17 2 100 150 125 4.5 20 30 25 6 17 25 21 2 100 150 125 4.5 20 30 25 6 17 25 21 2 0 0 0 4.5 0 0 0 6 0 0 0 UNIT MHz ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 5 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 6.6 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Section 7) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLR Any tpd CLK Any tt Any VCC (V) TA = 25°C SN54HC174 MAX MIN SN74HC174 MIN TYP MAX MIN 2 6 9 4.2 5 4.5 31 44 21 25 6 36 50 25 29 MAX UNIT MHz 2 58 160 240 200 4.5 17 32 48 40 6 14 27 41 34 2 58 160 240 200 4.5 17 32 48 40 6 14 27 41 34 2 38 75 110 90 4.5 8 15 22 19 6 6 13 19 16 ns ns 6.7 Operating Characteristics Ta = 25℃ PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance per flip-flop No load Submit Document Feedback TYP 27 UNIT pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 7 Parameter Measurement Information tpd is the maximum between tPLH and tPHL Figure 7-1. Load Circuit Figure 7-2. Voltage Waveforms Pulse Durations Figure 7-3. Voltage Waveforms Setup and Hold and Input Rise and Fall Times Figure 7-4. Voltage Waveforms Propagation Delay and Output Transition Times A. CL includes probe and jig capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50% D. The outputs are measured one at a time with one input transition per measurement. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 7 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 8 Detailed Description 8.1 Overview These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. 8.2 Functional Block Diagram Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. 8.3 Device Functional Modes Table 8-1. Function Table (each flip-flop) INPUTS 8 OUTPUT Q CLR CLK D L X X L H ↑ H H H ↑ L L H L X Q0 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 9 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 10 Layout 10.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 9 SN54HC174, SN74HC174 www.ti.com SCLS119E – DECEMBER 1982 – REVISED FEBRUARY 2022 11 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC174 SN74HC174 PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 84073012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84073012A SNJ54HC 174FK 8407301EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407301EA SNJ54HC174J Samples 8407301FA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407301FA SNJ54HC174W Samples JM38510/65307BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65307BEA Samples M38510/65307BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65307BEA Samples SN54HC174J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC174J Samples SN74HC174D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC174N Samples SN74HC174NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC174N Samples SN74HC174NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC174 Samples SN74HC174PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 Samples SNJ54HC174FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84073012A SNJ54HC 174FK Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 6-Nov-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54HC174J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407301EA SNJ54HC174J Samples SNJ54HC174W ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407301FA SNJ54HC174W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of