SN54HC175, SN74HC175
SCLS299F – JANUARY 1996 – REVISED JUNE 2022
SNx4HC175 Quadruple D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
•
•
•
•
These positive-edge-triggered D-type flip-flops have a
direct clear (CLR) input. The ’HC175 devices feature
complementary outputs from each flip-flop.
Wide operating voltage range of 2 V to 6 V
Outputs can drive up to 10 LSTTL Loads
Low power consumption, 80-μA max ICC
Contain four flip-flops with double-rail outputs
Typical tpd = 13 ns
±4-mA output drive at 5 V
Low input current of 1 μA max
2 Applications
•
•
•
Buffer/storage registers
Shift registers
Pattern generators
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN54HC175J
CDIP (16)
24.38 mm × 6.92 mm
SN74HC175D
SOIC (16)
9.90 mm × 3.90 mm
SN74HC175DBR
SSOP (16)
6.20 mm × 5.30 mm
SN74HC175N
PDIP (16)
19.31 mm × 6.35 mm
SN74HC175NSR
SO (16)
6.20 mm × 5.30 mm
SN74HC175PW
TSSOP (16)
5.00 mm × 4.40 mm
SNJ54HC175FK
LCCC (20)
8.89 mm × 8.45 mm
SNJ54HC175W
CFP (16)
10.16 mm × 6.73 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC175, SN74HC175
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SCLS299F – JANUARY 1996 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 Recommended Operating Conditions(1) .................... 4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Timing Requirements.................................................. 5
6.6 Switching Characteristics ...........................................6
6.7 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Device Functional Modes............................................8
9 Power Supply Recommendations..................................9
10 Layout.............................................................................9
10.1 Layout Guidelines..................................................... 9
11 Device and Documentation Support..........................10
11.1 Receiving Notification of Documentation Updates.. 10
11.2 Support Resources................................................. 10
11.3 Trademarks............................................................. 10
11.4 Electrostatic Discharge Caution.............................. 10
11.5 Glossary.................................................................. 10
12 Mechanical, Packaging, and Orderable
Information.................................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2022) to Revision F (June 2022)
Page
• Junction-to-ambient thermal resistance values increased. D was 73 is now 117.2, DB was 67 is now 102.7, N
was 82 is now 60.5, NS was 64 is now 88.6, PW was 108 is now 137.5........................................................... 4
Changes from Revision D (September 2003) to Revision E (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS299F – JANUARY 1996 – REVISED JUNE 2022
5 Pin Configuration and Functions
J, W, D, DB, N, NS, or PW Package
16-Pin CDIP, CFP, SOIC, SSOP, PDIP, SO, or TSSOP
Top View
NC - No internal connection
FK Package
20-Pin LCCC
Top View
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
℃
150
℃
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Recommended Operating Conditions(1)
SN54HC175
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
SN74HC175
MIN
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
5
6
3.15
4.2
4.2
VCC = 4.5 V
0
0.5
0.5
1.35
1.35
Operating free-air temperature
0
VCC
0
V
VCC
V
500
500
400
400
125
V
VCC
1000
−55
V
1.8
VCC
1000
Input transition rise/fall time VCC = 4.5 V
UNIT
V
1.8
0
VCC = 6 V
(1)
2
3.15
VCC = 2 V
TA
MAX
1.5
VCC = 6 V
tt
NOM
1.5
VCC = 2 V
VIL
MIN
−40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.3 Thermal Information
THERMAL METRIC
4
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal
(1)
resistance
117.2
102.7
60.5
88.6
137.5
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
77.2
48.6
48
46.2
75.3
°C/W
RθJB
Junction-to-board thermal
resistance
75.6
54.4
40.5
50.8
82.2
°C/W
ψJT
Junction-to-top characterization
parameter
38.1
11.6
27.4
13.4
25.1
°C/W
ψJB
Junction-to-board
characterization parameter
75.3
53.6
40.3
50.4
81.8
°C/W
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6.3 Thermal Information (continued)
THERMAL METRIC
RθJC(bot)
(1)
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
N/A
N/A
N/A
N/A
N/A
°C/W
Junction-to-case (bottom)
thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −20 μA
VOH
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
VI = VCC or 0,
MAX
MIN
MAX
UNIT
V
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
μA
10
10
10
pF
IOL = 5.2 mA
VI = VCC or 0
MIN
IOL = 20 μA
VI = VIH or VIL
II
MAX
SN74HC175
TYP
IOH = −5.2 mA
ICC
SN54HC175
MIN
VI = VIH or VIL
IOH = −4 mA
VOL
TA = 25°C
VCC
IO = 0
6V
Ci
2 V to 6 V
3
V
6.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
TA = 25°C
MIN
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK ↑
CLR inactive
MIN
SN74HC175
MAX
MIN
MAX
2V
6
4.2
5
4.5 V
31
21
25
6V
CLR low
SN54HC175
MAX
36
25
UNIT
MHz
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
ns
ns
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6.5 Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
VCC
th
Hold time, data after CLK ↑
MIN
SN54HC175
MAX
MIN
SN74HC175
MAX
MIN
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
UNIT
MAX
ns
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLR
Any
tpd
CLK
Any
tt
Any
VCC
TA = 25°C
MIN
TYP
SN54HC175
MAX
MIN
SN74HC175
MAX
MIN
2V
6
12
4.2
5
4.5 V
31
50
21
25
6V
36
60
25
29
UNIT
MAX
MHz
2V
52
150
255
190
4.5 V
15
30
45
38
6V
13
26
38
32
2V
58
150
255
190
4.5 V
16
30
45
38
6V
13
26
38
32
2V
38
75
110
90
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
6.7 Operating Characteristics
TA = 25℃
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance per flip-flop
No load
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TYP
30
UNIT
pF
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SCLS299F – JANUARY 1996 – REVISED JUNE 2022
7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 7-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 7-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
50%
90%
VOH
90%
10%
50%
10%
tr(1)
(1)
VOH
Output
0V
tf(1)
Output
50%
(1)
VCC
90%
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
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8 Detailed Description
8.1 Overview
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
8.2 Functional Block Diagram
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
8.3 Device Functional Modes
Table 8-1. Function Table
(each flip-flop)
INPUTS
8
OUTPUTS
CLR
CLK
D
Q
Q
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
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SCLS299F – JANUARY 1996 – REVISED JUNE 2022
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
84089012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84089012A
SNJ54HC
175FK
8408901EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408901EA
SNJ54HC175J
Samples
8408901FA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408901FA
SNJ54HC175W
Samples
JM38510/65308BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65308BEA
Samples
M38510/65308BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65308BEA
Samples
SN54HC175J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC175J
Samples
SN74HC175D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC175N
Samples
SN74HC175NE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC175N
Samples
SN74HC175NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SN74HC175PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC175
Samples
SNJ54HC175FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84089012A
SNJ54HC
175FK
SNJ54HC175J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408901EA
SNJ54HC175J
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
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Orderable Device
11-Aug-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54HC175W
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408901FA
SNJ54HC175W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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